Main Content

Dual Port RAM

Dual port RAM with two output ports

  • Library:
  • HDL Coder / HDL RAMs

  • Dual Port RAM block

Description

The Dual Port RAM block models a RAM that supports simultaneous read and write operations, and has both a read data output port and write data output port. You can use this block to generate HDL code that maps to RAM in most FPGAs.

If you do not need to use the write output data, wr_dout, you can achieve better RAM inference with synthesis tools by using the Simple Dual Port RAM block.

Read-During-Write Behavior

During a write, new data appears at the output of the write port (wr_dout) of the Dual Port RAM block. If a read operation occurs simultaneously at the same address as a write operation, old data appears at the read output port (rd_dout).

Ports

Input

expand all

Data that you write into the RAM memory location when wr_en is true. The data inherits the width and data type from the input signal. wr_din can be a double, single, integer, or a fixed-point (fi) object, and can be real or complex.

Data type: scalar fixed point, integer, or complex

Data Types: int8 | int16 | int32 | int64 | Boolean | fixed point

Address that you write the data into when wr_en is true. This value can be either fixed-point(fi) or integer, must be unsigned, and have a fraction length of 0.

Data Types: uint8 | uint16 | uint32 | uint64 | fixed point

When wr_en is true, the RAM writes the data into the memory location that you specify.

Data Types: Boolean

Address that you read the data from. This value can be either fixed-point(fi) or integer, must be unsigned, and have a fraction length of 0.

Data Types: uint8 | uint16 | uint32 | uint64 | fixed point

Output

expand all

Output data from write address, wr_addr.

Data Types: single | double | int8 | int16 | int32 | int64 | uint8 | uint16 | uint32 | uint64 | Boolean | fixed point | enumerated | bus

Output data from read address, rd_addr.

Data Types: single | double | int8 | int16 | int32 | int64 | uint8 | uint16 | uint32 | uint64 | Boolean | fixed point | enumerated | bus

Parameters

expand all

Minimum bit width is 2, and maximum bit width is 29.

Programmatic Use

Block parameter: ram_size
Type: string scalar | character vector
Value: A minimum value of 2 and maximum value of 29
Default: '8'

Algorithms

expand all

HDL code generated for RAM blocks has:

  • A latency of one clock cycle for read data output.

  • No reset signal, because some synthesis tools do not infer a RAM from HDL code if it includes a reset.

Code generation for a RAM block creates a separate file, blockname.ext. blockname is derived from the name of the RAM block. ext is the target language file name extension.

Extended Capabilities

C/C++ Code Generation
Generate C and C++ code using Simulink® Coder™.

Version History

Introduced in R2014a