CIC Decimator

Decimate signal using CIC filter

• 

×

Libraries:
DSP HDL Toolbox / Filtering

Description

The CIC Decimator block decimates an input signal by using a cascaded integrator-comb (CIC) decimation filter. CIC decimation filters are a class of linear phase finite impulse response (FIR) filters consisting of a comb part and an integrator part. The CIC decimation filter structure consists of N sections of cascaded integrators, a rate change factor of R, and N sections of cascaded comb filters. For more information about CIC decimation filters, see Algorithms.

The block supports these combinations of input and output data.

• Scalar input and scalar output — Support for fixed and variable decimation rates

• Vector input and scalar output — Support for fixed decimation rates only

• Vector input and vector output — Support for fixed decimation rates only

The block provides an architecture suitable for HDL code generation and hardware deployment.

Note

You can also generate HDL code for this hardware-optimized algorithm, without creating a Simulink^® model, by using the DSP HDL IP Designer app. The app provides the same interface and configuration options as the Simulink block.

Examples

Implement CIC Decimator Filter for HDL

Filter and downsample data by using the CIC Decimator block.

• Open Script

Implement Digital Downconverter for FPGA

Design a digital downconverter (DDC) for LTE on FPGAs.

• Open Script

Ports

Input

data — Input data

scalar | column vector

Input data, specified as a scalar or a column vector with a length from 1 to 64. The input data must be a signed integer or a signed fixed point with a word length less than or equal to 32. The Decimation factor (R) parameter must be an integer multiple of the input frame size.

While processing the input data, the block implements the rounding method Floor and the overflow action Wrap. For more details, see Rounding Modes and Overflow Handling.

Data Types: int8 | int16 | int32 | signed fixed point
Complex Number Support: Yes

valid — Indicates valid input data

scalar

Control signal that indicates if the input data is valid. When valid is 1 (true), the block captures the values from the input data port. When valid is 0 (false), the block ignores the values from the input data port.

Data Types: Boolean

R — Variable decimation rate

scalar

Use this port to dynamically specify the variable decimation rate during run time.

This value must have the data type fixdt(0,12,0) and it must be an integer in the range from 1 to the Decimation factor (Rmax) parameter value.

Dependencies

To enable this port, on the Main tab, set the Decimation factor source parameter to Input port.

Data Types: fixdt(0,12,0)

reset — Clears internal states

scalar

Control signal that clears internal states. When reset is 1 (true), the block stops the current calculation and clears internal states. When the reset is 0 (false) and the input valid is 1 (true), the block captures data for processing.

For more reset considerations, see the Reset Signal section on the Hardware Control Signals page.

Dependencies

To enable this port, on the Control Ports tab, select the Enable reset input port parameter.

Data Types: Boolean

Output

data — CIC-decimated output data

scalar | column vector

The block returns filtered output data as a scalar or a column vector with a length from 1 to 64. You can define the data type of this output by setting the Output data type parameter on the Data Types tab.

Data Types: int8 | int16 | int32 | signed fixed point
Complex Number Support: Yes

valid — Indicates valid output data

scalar

Control signal that indicates if the data from the output data port is valid. When valid is 1 (true), the block returns valid data from the output data port. When valid is 0 (false), the values from the output data port are not valid.

Data Types: Boolean

Parameters

Main

Decimation factor source — Source of decimation factor

Property (default) | Input port

Select whether the block operates with a fixed or variable decimation rate.

• Property — Use a fixed decimation rate specified from the Decimation factor (R) parameter.

• Input port — Use a variable decimation rate specified from the R input port.

Note

For vector inputs, the block does not support variable decimation.

Decimation factor (R) — Decimation factor

2 (default) | integer from 1 to 2048

Specify the decimation factor rate at which the block decimates the input.

Dependencies

To enable this parameter, set the Decimation factor source parameter to Property.

Decimation factor (Rmax) — Upper bound of variable decimation factor

2 (default) | integer from 1 to 2048

Specify the upper bound of the range of valid values for the R input port.

Note

For vector inputs, the block does not support variable decimation.

Dependencies

To enable this parameter, set the Decimation factor source parameter to Input port.

Differential delay (M) — Differential delay

1 (default) | 2

Specify the differential delay of the comb part of the block.

Number of sections (N) — Number of integrator and comb sections

2 (default) | 1 | 3 | 4 | 5 | 6

Specify the number of sections in either the comb part or the integrator part of the block.

Gain correction — Output gain compensation

off (default) | on

Select this parameter to compensate for the output gain of the block.

The latency of the block changes depending on the type of input, the decimation you specify, the number of sections, and the value of this parameter. For more information on the latency of the block, see Latency.

Data Types

Output data type — Data type of output

Full precision (default) | Same word length as input | Minimum section word lengths

Select the data type for the output data.

• Full precision — The output data type has a word length equal to the input word length plus gain bits.

• Same word length as input — The output data type has a word length equal to the input word length.

• Minimum section word lengths — The output data type uses the word length you specify in the Output word length parameter. When you select this option, the block applies the pruning algorithm. For more information about the pruning algorithm, see [1].

Output word length — Word length of output

16 (default) | integer from 2 to 104

Specify the word length of the output.

Note

When this value is 2, 3, 4, 5, or 6, the block can overflow the output data.

Dependencies

To enable this parameter, set the Output data type parameter to Minimum section word lengths.

Control Ports

Enable reset input port — Reset signal

off (default) | on

Select this parameter to enable the reset input port. The reset signal implements a local synchronous reset of the data path registers.

For more reset considerations, see Tips.

Use HDL global reset — Option to connect data path registers to generated HDL global reset signal

off (default) | on

Select this parameter to connect the generated HDL global reset signal to the data path registers. This parameter does not change the appearance of the block or modify simulation behavior in Simulink. When you clear this parameter, the generated HDL global reset clears only the control path registers. The generated HDL global reset can be synchronous or asynchronous depending on the HDL Code Generation > Global Settings > Reset type parameter in the model Configuration Parameters.

For more reset considerations, see Tips.

Tips

Reset Behavior

• By default, the CIC Decimator block connects the generated HDL global reset to only the control path registers. The two reset parameters, Enable reset input port and Use HDL global reset, connect a reset signal to the data path registers. Because of the additional routing and loading on the reset signal, resetting data path registers can reduce synthesis performance.

• The Enable reset input port parameter enables the reset port on the block. The reset signal implements a local synchronous reset of the data path registers. For optimal use of FPGA resources, this option does not connect the reset signal to registers targeted to the DSP blocks of the FPGA.

• The Use HDL global reset parameter connects the generated HDL global reset signal to the data path registers. This parameter does not change the appearance of the block or modify simulation behavior in Simulink. The generated HDL global reset can be synchronous or asynchronous depending on the HDL Code Generation > Global Settings > Reset type parameter in the model Configuration Parameters. Depending on your device, using the global reset might move registers out of the DSP blocks and increase resource use.

• When you select the Enable reset input port and Use HDL global reset parameters together, the global and local reset signals clear the control and data path registers.

Reset Considerations for Generated Test Benches

• FPGA-in-the-loop (FIL) initialization provides a global reset but does not automatically provide a local reset. With the default reset parameters, the data path registers that are not reset can result in FIL mismatches if you run the FIL model more than once without resetting the board. Select Use HDL global reset to reset the data path registers automatically, or select Enable reset input port and assert the local reset in your model so the reset signal becomes part of the Simulink FIL test bench.

• The generated HDL test bench provides a global reset but does not automatically provide a local reset. With the default reset parameters and the default register reset Configuration Parameters, the generated HDL code includes an initial simulation value for the data path registers. However, if you are concerned about X-propagation in your design, you can set the HDL Code Generation > Global Settings > Coding style > No-reset register initialization parameter in Configuration Parameters to Do not initialize. In this case, with the default block reset parameters, the data path registers that are not reset can cause X-propagation on the data path at the start of HDL simulation. Select Use HDL global reset to reset the data path registers automatically, or select Enable reset input port and assert the local reset in your model so the reset signal becomes part of the generated HDL test bench.

Algorithms

CIC Decimation Filter

The transfer function of a CIC decimation filter is

$$H(z)={\left[{\displaystyle \sum _{k=0}^{RM-1}{z}^{-k}}\right]}^N=\frac{{\left(1-z^{-RM}\right)}^N}{{\left(1-z^{-1}\right)}^N}=\frac{1}{{\left(1-z^{-1}\right)}^N}·\frac{{\left(1-z^{-RM}\right)}^N}{1}=H_{\text{I}}{}^N(z)·H_{\text{c}}{}^N(z).$$

• H_I is the transfer function of the integrator part of the CIC filter.

• H_C is the transfer function of the comb part of the CIC filter.

• N is the number of sections. The number of sections in a CIC filter is defined as the number of sections in either the comb part or integrator part of the filter. This value does not represent the total number of sections throughout the entire filter.

• R is the decimation factor.

• M is the differential delay.

CIC Filter Structure

The CIC Decimator block has the CIC filter structure shown in this figure. The structure consists of N sections of cascaded integrators, a rate change factor of R, and N sections of cascaded comb filters [1].

You can locate the unit delay in the integrator part of the CIC filter in either the feedforward or feedback path. These two configurations yield an identical filter frequency response. However, the numerical outputs from these two configurations are different due to the latency of the block. Because this configuration is preferred for HDL implementation, this block puts the unit delay in the feedforward path of the integrator.

Fixed and Variable Decimation

The block downsamples the integrator stage output using R, either based on the fixed decimation rate provided using the Decimation factor (R) parameter or the variable decimation rate provided using the R input port. At the downsampler stage, the block uses a counter to count the valid input samples, which depend on the decimation rate. Whenever the decimation rate changes, the block resets and starts a new calculation from the next sample. This mechanism prevents the block from accumulating false values. Then, the block provides the decimated output to the comb part of the CIC filter.

Gain Correction

The gain of the block is given by $$Gain={(R\text{x}M)}^N$$.

• R is the Decimation factor (R) parameter value.

• M is the Differential delay (M) parameter value.

• N is the Number of sections (N) parameter value.

The block implements gain correction in two parts: coarse gain and fine gain. In coarse gain correction, the block calculates the shift value, adds the shift value to the fractional bits to create a numeric type, and performs a bit-shift left and reinterpretcast. In fine gain correction, the block divides the remaining gain with the coarse gain if the gain is not a power of 2. Then, the block multiplies the corrected coarse gain corrected value with the inverse value of the fine gain. Before the block starts processing, all possible shift and fine gain values are precalculated and stored in an array.

You can modify this equation as $$Gain=2^{cGain}\text{x}fGain$$. In this equation, cGain is the coarse gain, and fGain is the fine gain. These gains are given by these equations.

• $$cGain=floor({\log }_{2}Gain)$$

• $$fGain=Gain/2^{cGain}=Gain\text{x}{2}^{-cGain}{}^{}$$

To perform gain correction when the Decimation factor source parameter is set to Input port, the block sets the output data type configured with the maximum decimation rate and bit-shifts left for all of the values under the maximum decimation rate. The bit-shift value is equal to $$Maximumgain-{\log }_2(currentgain)$$.

Output Data Type

The block outputs data based on the output data type selection. Consider a block with R, M, and N values of 8, 1, and 3, respectively, and an input width of 16. The output word length is calculated as $$B_{\text{Out}}=B_{\text{In}}+[{\log }_2(Gain)]$$.

• $$Gain={(R\text{x}M)}^N$$

• B_In is the input word length.

• B_Out is the output word length.

When you set the Output data type parameter to Full precision, the block outputs data with a word length of 25 by adding 9 gain bits to the input word length of 16.

When you set the Output data type parameter to Same word length as input, the block outputs data with a word length of 16, which is the same length as the input word length. The internal integrator and comb stages use the full-precision data type with 25 bits.

When you set the Output data type parameter to Minimum section word lengths and the Output word length parameter to 16, the block outputs data with a word length of 16. In this case, the block changes the bit width at each stage, based on the pruning algorithm.

If the Output word length parameter value is less than the number of bits required at the block output, the least significant bits (LSBs) at the earlier stages are pruned. The Hogenauer algorithm [1] provides the number of LSBs to discard at each stage. This algorithm minimizes the loss of information in the output data.

Latency

The latency of the block changes depending on the type of input, the decimation you specify, the number of sections, and the value of the Gain correction parameter. This table shows the latency of the block. N is the number of sections and vecLen is the length of the vector.

Input Data	Output Data	Decimation Type	Gain Correction	Latency in Clock Cycles
Scalar	Scalar	Fixed	off	3 + N. When R = 1, 2 + N.
			on	3 + N + 9. When R = 1, 2 + N + 9.
Scalar	Scalar	Variable	off	4 + N. When Rmax = 1, 3 + N.
			on	4 + N + 9. When Rmax = 1, 3 + N + 9.
Vector	Scalar	Fixed	off	floor((vecLen – 1) x (N/vecLen)) + 1 + N + (2 + (vecLen + 1) x N
			on	floor((vecLen – 1) x (N/vecLen)) + 1 + N + (2 + (vecLen + 1) x N) + 9
Vector	Vector	Fixed	off	floor((vecLen – 1) x (N/vecLen)) + 1 + N + (2 + (vecLen + 1) x N
			on	floor((vecLen – 1) x (N/vecLen)) + 1 + N + (2 + (vecLen + 1) x N) + 9

Note

For vector inputs, the block does not support variable decimation.

Scalar Input

This section shows the output of the block for a scalar input with different R, M, and N values.

This figure shows the output of the block with the default configuration (that is, with a fixed decimation rate and R, M, and N values of 2, 1, and 2, respectively). The block returns valid output data at every second cycle based on the fixed Decimation factor (R) parameter value of 2. The latency of the block is 5 clock cycles and is calculated as 3 + N, where N is the number of sections.

This figure shows the output of the block with a fixed decimation rate, R, M, and N values of 8, 1, and 3, respectively, and the Gain correction parameter selected. The block returns valid output data at every eighth cycle based on the fixed Decimation factor (R) parameter value of 8. The latency of the block is 15 clock cycles and is calculated as 3 + N + 9, where N is the number of sections.

This figure shows the output of the block with variable decimation rate (R input port) values of 2, 4, and 8 and with M and N values of 1 and 3, respectively. In this case, the Gain correction parameter is cleared. The block returns valid output data at the second, fourth, and eighth cycles corresponding to the R port values 2, 4, and 8, respectively. The block accepts R port value changes only when the valid input port is 1. The latency of the block is 7 clock cycles and is calculated as 4 + N, where N is the number of sections.

Vector Input

This section shows the output of the block for a vector input with different R, M, and N values.

This figure shows the output of the block for a two-element column vector input with the default configuration, (that is, with a fixed decimation rate and R, M, and N values of 2, 1, and 2, respectively). The latency of the block is 12 clock cycles.

This figure shows the output of the block for an eight-element column vector input with a fixed decimation rate, R, M, and N values of 8, 1, and 3, respectively, and the Gain correction parameter selected. The latency of the block is 44 clock cycles.

Performance

The performance of the synthesized HDL code varies with your target and synthesis options. It also varies based on the input data type.

This table shows the resource and performance data synthesis results of the block for a scalar input of type fixdt(1,16,0) with fixed and variable decimation rates and for a two-element column vector input with a fixed decimation rate when R, M, and N are 2, 1, and 2, respectively. The generated HDL is targeted to the AMD^® Zynq^®- 7000 ZC706 Evaluation Board.

Input Data	Decimation Type	Slice LUTs	Slice Registers	Maximum Frequency in MHz
Scalar	Fixed rate	101	166	711.74
	Variable rate	206	186	441.70
Vector	Fixed rate	218	627	624.61

The resources and frequencies vary based on the type of input data and the values of R, M, and N, as well as other parameter values selected in the block mask. Using a vector input can increase the throughput, however, doing so also increases the number of hardware resources that the block uses.

References

[1] Hogenauer, E. “An Economical Class of Digital Filters for Decimation and Interpolation.” IEEE Transactions on Acoustics, Speech, and Signal Processing 29, no. 2 (April 1981): 155–62. https://doi.org/10.1109/TASSP.1981.1163535.

Extended Capabilities

C/C++ Code Generation

Generate C and C++ code using Simulink® Coder™.

This block supports C/C++ code generation for Simulink accelerator and rapid accelerator modes and for DPI component generation.

HDL Code Generation

Generate VHDL, Verilog and SystemVerilog code for FPGA and ASIC designs using HDL Coder™.

HDL Coder™ provides additional configuration options that affect HDL implementation and synthesized logic.

HDL Architecture

This block has one default HDL architecture.

HDL Block Properties

ConstrainedOutputPipeline	Number of registers to place at the outputs by moving existing delays within your design. Distributed pipelining does not redistribute these registers. The default is 0. For more details, see ConstrainedOutputPipeline (HDL Coder).
InputPipeline	Number of input pipeline stages to insert in the generated code. Distributed pipelining and constrained output pipelining can move these registers. The default is 0. For more details, see InputPipeline (HDL Coder).
OutputPipeline	Number of output pipeline stages to insert in the generated code. Distributed pipelining and constrained output pipelining can move these registers. The default is 0. For more details, see OutputPipeline (HDL Coder).

Version History

Introduced in R2019b

R2022a: Moved to DSP HDL Toolbox from DSP System Toolbox

Before R2022a, this block was named CIC Decimation HDL Optimized and was included in the DSP System Toolbox™ DSP System Toolbox HDL Support library.

R2022a: Changes to decimation factor parameters

You can now set the decimation factor to 1. In previous releases, a decimation factor of 1 was invalid.

Configuration	Before R2022a	After 2022a
Variable decimation factor	Select the Variable decimation parameter and set the Decimation factor (R) parameter to the maximum expected decimation factor.	Set the Decimation factor source parameter to Input port and set the Decimation factor (Rmax) parameter to the maximum expected decimation factor. The decimFactor port is renamed to R.
Fixed decimation factor	Clear the Variable decimation parameter and set the Decimation factor (R) parameter to the desired decimation factor.	Set the Decimation factor source parameter to Property and set the Decimation factor (R) to the desired decimation factor.

R2021b: High-throughput interface

The block accepts and returns a column vector of elements that represent samples in time. The input vector can contain up to 64 samples. When you use frame-based input, you must use a fixed decimation factor.

R2020a: Gain correction and programmable decimation factor

You can optionally enable automatic gain correction. You can also specify the decimation factor as an input port.