User Stories

Siglead Shortens Development Time for FPGA and ASIC Signal Processing Systems for Storage Devices


Speed the development of FPGA and ASIC signal processing components for mass storage devices


Use MATLAB, Simulink, and HDL Coder to develop algorithms, evaluate design alternatives, and automatically generate HDL code


  • Development time cut by about 75%
  • Design modifications completed within hours
  • Engineering productivity increased

“MATLAB, Simulink, and HDL Coder are indispensable for us because we simulate, debug, and verify our design as an executable specification and then generate the initial HDL in almost no time.”

Atsushi Esumi, Siglead
First engineering sample of Siglead’s SSD controller.

Today’s storage devices, including solid state drives (SSDs) and hard disk drives (HDDs), require advanced signal processing subsystems for high-speed data encryption and error correction. In many organizations, engineers develop the initial algorithms for these subsystems in C or C++. The algorithms are then used as reference models for writing and verifying HDL code for FPGA or ASIC implementation. Translating the reference C algorithms to HDL is both time-consuming and error-prone, as engineers have to map the sequential behavior of C to the parallel behavior of hardware. This process makes design iterations very difficult.

Engineers at Siglead Inc. use Model-Based Design with MATLAB® and Simulink® to bridge the gap between algorithm development and HDL implementation. “Moving from a reference model designed by an algorithm engineer to the HDL or RTL implementation developed by hardware engineers can be difficult because the engineers come from such different backgrounds,” says Atsushi Esumi, president and CEO at Siglead. “With MATLAB and Simulink, our algorithm engineers can generate HDL on their own. This accelerates development and enables our hardware engineers to concentrate on other critical design tasks, such as speed and size optimization.”


Siglead wanted to shorten development time for two core signal processing systems: an error-correction system for an HDD that would initially be implemented on an FPGA and an AES scrambling ASIC for an SSD.

On the HDD project, Siglead needed to evaluate several designs to ensure that the FPGA implementation was as compact as possible. On the SSD project, real-time performance and timing were crucial to meeting the component’s 6.4 Gbps requirement.

Both projects would have been exceptionally difficult using Siglead’s traditional process of developing a reference model in C and then hand-coding HDL. “Our systems include complex signal flows and feedback loops that are difficult to describe in C,” Esumi explains. “Even if we had added engineers, we could not have completed the projects on time because a larger team would add to the communication challenges.”

In the past, it was difficult to determine the cause of any differences between the reference model results and the HDL results. System-level verification of bit error rate and other performance metrics was also a challenge.


Siglead engineers used MATLAB, Simulink, and HDL Coder to model, simulate, verify, and automatically generate synthesizable HDL code for the signal processing components in their SSD and HDD systems.

For the HDD signal processing component, the engineers used Simulink to model several designs, including parallel architectures, which assembled the sampled signals from the drive head into data.

The Simulink model served as an executable specification throughout the project and enabled the team to verify the functionality of early designs through simulation.

Using Fixed-Point Designer, the team converted the floating-point design to fixed point. They then optimized fixed-point data types to complete the cycle-accurate model.

The engineers generated bit-true synthesizable VHDL® code from the fixed-point Simulink model using HDL Coder and deployed it on a Xilinx® Spartan®-6 FPGA. They verified the FPGA implementation by comparing its output with output from the cycle-accurate Simulink model. For the SSD controller, Siglead engineers developed and tested the key encryption algorithms in MATLAB. They then used a MATLAB Function block to incorporate the algorithms into a Simulink system model.

From that point on, the engineers followed the same workflow that they had used on the HDD project. After verifying the floating-point model, they converted it to fixed point using Fixed-Point Designer. They then generated HDL code with HDL Coder and simulated the code with their HDL simulators.

Siglead completed both projects on schedule. The final ASIC design for the SSD controller has been submitted to the foundry to produce an engineering sample. The design for the HDD component has moved into production.


  • Development time cut by about 75%. “By automatically generating HDL code from a verified, cycle-accurate Simulink model, we eliminated the time required to write the HDL by hand and verify its functionality,” says Esumi. “We estimated that the HDD project would take up to four months, but we completed it in one month. The SSD project, which would have taken two months using our previous process, was completed in one week.”

  • Design modifications completed within hours. “With MATLAB, Simulink, and HDL Coder we have greatly accelerated design iterations,” notes Esumi. “On the SSD project, when we modified the design to improve performance via parallelization, we completed the modification in three hours. With our previous process, we would have needed three days.”

  • Engineering productivity increased. “MATLAB and Simulink enable us to spend more time on productive engineering work, including developing algorithms and exploring design alternatives,” says Esumi. “The SSD’s complex signal processing algorithms were developed by just two engineers, who implemented the design themselves in RTL using HDL Coder.”