Jeff Miller, MathWorks
Jack Erickson, MathWorks
Adding LTE connectivity to a device requires implementing the system-level algorithms in FPGA or ASIC hardware while maintaining compliance with the standard. This webinar will show how to:
About the Presenters
Jeff Miller joined the MathWorks in 2005. As a senior applications engineer, Jeff focuses on supporting customers for adopting HDL code generation and LTE technology. Customer projects have included HDL designs for high performance FFT, FIR, Matrix Mathematics, Encryption, Custom Floating Point, and LTE receivers. As an Application Engineer (2006-2011), Jeff covered a breadth of Signal Processing and Communications topics including radar, audio, fixed point design, RF electronics, Analog Mixed Signal, etc. Jeff worked at Applied Signal Technology from 1998-2000 doing Signal Intelligence Work, and at Morphics Technology 2000-2001 doing commercial wireless communications. Jeff has a Master’s of Electrical Engineering from Georgia Tech (2003) and a Master’s of Education from the University of Arizona (2005).
Jack Erickson is responsible for product marketing and product management for the HDL product family at MathWorks. Prior to joining MathWorks, he spent over 20 years at Cadence Design Systems, Inc., as an applications engineer and in product marketing for simulation, RTL synthesis, and high-level synthesis. He has a BSEE from Tufts University and an MBA from Worcester Polytechnic Institute.