Objective: Prepare a Simulink model for HDL code generation. Generate HDL code and testbench for simple models requiring no optimization.

• Preparing Simulink Models for HDL Code Generation
• Generating HDL code
• Generating a test bench
• Verifying generated HDL code with an HDL simulator

Objective: Establish correspondence between generated HDL code and specific Simulink blocks in the model. Use Fixed-Point Tool to finalize fixed point architecture of the model.

• Linking generated HDL code to specific Simulink blocks
• Improving the efficiency and accuracy of the HDL code with Fixed-Point Tool

Objective: Generate HDL code for multirate designs

• Preparing a multirate model for generating HDL code
• Generating HDL code with single or multiple clock pins

Objective: Use pipelines to meet design timing requirements. Use specific hardware implementations and share resources for area optimization.

• Generating HDL code with the HDL Workflow Advisor
• Meeting timing requirements via pipelining
• Choosing specific hardware implementations for compatible Simulink blocks
• Sharing FPGA/ASIC resources in subsystems
• Verifying that the optimized HDL code is bit-true cycle-accurate

Objective: Generate HDL code when part of the design is written in MATLAB using the MATLAB Function block. Use and adapt blocks from the design patterns library for your own design. Write MATLAB code for fixed point operations.

• Using the design patterns library
• Generating HDL code from MATLAB Function blocks

Objective: Incorporate hand-written HDL code and/or vendor party IP in your design.

• Interfacing external HDL code
• Interfacing vendor-party IP

Objective: Verify your HDL code using an HDL simulator in the Simulink model.

• Verifying an HDL component using Simulink