Simulink Verification and Validation™ lets you link Simulink® and Stateflow® objects to text in requirements documents. The toolbox supports requirements stored in IBM® Rational® DOORS®, Microsoft® Word, Microsoft Excel®, PDF, or HTML files. You can apply keywords and descriptions to the links in Simulink to better document your design. The interface can be customized to support various document types and requirements management systems.
Simulink Verification and Validation provides bidirectional traceability by placing links to Simulink artifacts in your requirements document. The tool synchronizes your links in requirements management products such as DOORS. To confirm that your requirements links are consistent with their source documents, you can check for deleted or modified requirements. An application program interface (known as the Requirements Management Interface) can help you automate requirements traceability analysis.
Tools that help you scale testing and generate code also support requirements linking. You can link requirements to test cases, test suites, and test sequences in Simulink Test™, and access links from the Simulink canvas or the test manager. Code generated from Embedded Coder®, HDL Coder™, or Simulink PLC Coder™ can be hyperlinked from the code generation report to the requirements document. These links are presented as comment labels in the code. The hyperlinks in the code generation report provide direct navigation from code to requirements.
Visit the MathWorks Connections Program for third-party requirements management solutions that support Simulink Verification and Validation.
Simulink Verification and Validation provides a library of ready-to-use checks so you can verify compliance with style guidelines and modeling standards. The checks are preconfigured to support MathWorks Automotive Advisory Board (MAAB) Style Guidelines and the DO-178, ISO 26262, IEC 61508, and IEC 62304 standards for developing high-integrity software. You can run individual or group checks with the Model Advisor tool. Each check comes with detailed documentation and recommendations for resolving identified issues, warnings, and errors. You are given the option to let the tool perform corrective fixes to address identified issues.
Simulink Verification and Validation supports your development processes by checking that your model is compatible with downstream tools. For example, you can confirm that your model is compatible with tools such as Simulink Code Inspector™ and Simulink Design Verifier™. The Model Advisor feature can display design issues, such as dead logic and division by zero errors, detected by these tools. You can generate model metrics to help assess your model for size, complexity, and readability. These metrics provide guidance for developing clear and unambiguous models that are compact, portable, and reviewable.
To ensure your model complies with your own standards or guidelines, you can use the Model Advisor APIs and Configuration Editor to create your own Model Advisor checks. You can also modify the built-in modeling compliance and industry standards to create your own custom verification checks. Similar to the built-in checks, these custom checks permit you to specify what actions you want the Model Advisor to take, such as producing an error or automatically applying fixes to your model.
To automate or speed up compliance verification, you can run checks in batch mode on a single machine or on multiple machines in parallel with Parallel Computing Toolbox™. View compliance check results within the Model Advisor or in the HTML report generated at the end of the analysis run.
You can use IEC Certification Kit (for ISO 26262 and IEC 61508) and DO Qualification Kit (for DO-178) to qualify Simulink Verification and Validation for supported industry standards, including DO-178, ISO 26262, and IEC 61508.
Simulink Verification and Validation produces model and code coverage reports to identify untested elements of your design. Coverage reports measure the degree to which your model is verified by a test case or test suite. The report determines how much a test case or test suite exercises execution pathways through the design. It provides a cumulative metric of executing logical conditions, switches, subsystems, and lookup table interpolation intervals in your model. In addition to model coverage, Simulink Verification and Validation produces coverage reports for C S-functions and for generated code that has been produced by Embedded Coder.
Models with high coverage metrics indicate that they have been more thoroughly tested. Simulink Verification and Validation produces coverage reports and displays coverage information directly on blocks and subsystems in your model. You can use this information to traverse the model and identify which aspects of your design lack coverage. You can then determine whether you need to modify the requirements, test cases, or design to meet your coverage goals.
Simulink Verification and Validation produces the following coverage metrics:
Execution coverage is the most basic form of model coverage. For each block or subsystem, execution coverage determines whether or not the item is executed during simulation.
Statement coverage is the basic form of code coverage for C S-functions and generated code. It identifies code statements that have been exercised.
Cyclomatic complexity measures the structural complexity of a model, approximating the McCabe complexity measure for code generated from the model.
Condition coverage examines blocks (or code) that output the logical combination of their inputs, such as the Logic block and Stateflow transitions.
Decision coverage examines items that represent decision points in a model, such as Simulink Switch blocks, Stateflow states, or conditional statements in code.
Lookup table coverage (LUT) records the frequency of usage for each interpolation interval. (A test case achieves full coverage if it executes each interpolation and extrapolation interval at least once.)
Modified condition/decision coverage (MC/DC) analyzes safety-critical software, as defined by RTCA DO-178, and determines whether the logical inputs have independently changed the output (for models and code).
Relational boundary coverage examines blocks, Stateflow charts and MATLAB® function blocks that have an explicit or implicit relational operation.
Saturate on integer overflow coverage records the number of times blocks such as the Abs block saturates on integer overflow.
Signal range coverage indicates the minimum and maximum values generated during simulation by each block output and for all Stateflow data objects.
Signal size coverage records the minimum, maximum, and allocated size for all variable-size signals in a model. Only blocks with variable-size output signals are included in the report.
Simulink Design Verifier coverage records model coverage data for the Simulink Design Verifier blocks and functions.