HDL Verifier™ automatically generates test benches for Verilog® and VHDL® design verification. You can use MATLAB® or Simulink® to directly stimulate your design and then analyze its response using HDL cosimulation or FPGA-in-the-loop with Xilinx® and Intel® FPGA boards. This approach eliminates the need to author standalone Verilog or VHDL test benches.
HDL Verifier also generates components that reuse MATLAB and Simulink models natively in simulators from Cadence®, Mentor Graphics®, and Synopsys®. These components can be used as verification checker models or as stimuli in more complex test-bench environments such as those that use the Universal Verification Methodology (UVM).
Discover more about HDL Verifier by exploring these resources.
Explore documentation for HDL Verifier functions and features, including release notes and examples.
Browse the list of available HDL Verifier functions.
View a Simulink library of blocks that HDL Verifier supports.
Browse the list of available HDL Verifier System objects™.
View system requirements for the latest release of HDL Verifier.
View articles that demonstrate technical advantages of using HDL Verifier.
Read how HDL Verifier is accelerating research and development in your industry.
Find answers to questions and explore troubleshooting resources.
Connect HDL Verifier to hardware platforms.
HDL Verifier requires MATLAB.
Use HDL Verifier to solve scientific and engineering challenges: