DSP HDL Toolbox™ provides pre-verified, hardware-ready Simulink® blocks and subsystems for developing signal processing applications such as wireless, radar, audio, and sensor processing. It includes templates for interfacing MATLAB® and Simulink as well as reference examples.
Using the toolbox you can model, explore, and simulate hardware architecture options for DSP algorithms. The IP blocks enable implementation for serial and parallel processing so you can explore the design space between resource usage, power, and gigasample-per-second (GSPS) throughput performance.
The toolbox algorithms let you generate readable, synthesizable code in VHDL® and Verilog® (with HDL Coder™). You can also generate SystemVerilog DPI verification components from designs that use these algorithms (with HDL Verifier™).
DSP HDL Blocks
Choose from a range of hardware-verified optimized library blocks to implement DSP filters and transforms on hardware.
Explore throughput options at gigasample-per-second (GSPS) rates by simply changing input data parallelism and specifying a supported architecture.
Design Tradeoff Exploration
Explore serial and parallel options for design tradeoffs such as power, throughput, and resource usage for various configurable architecture choices using built-in block parameters.
Model, simulate, and deploy radar, wireless, and other real-world applications requiring high-speed processing on FPGAs and SoCs.
DSP Algorithm Prototyping on FPGAs, ASICs, and SoCs
Use hardware-proven blocks together with HDL Coder to speed development of applications ready for prototyping on any FPGA platform.
Verification of HDL Designs via Cosimulation
With HDL Verifier, verify your generated HDL running in a supported EDA simulator or on an FPGA development kit, connected to your MATLAB or Simulink test environment.