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What to do after generating HDL code?
I am assuming you are using an evaluation FPGA board. Use traceability report to understand the elements of the generated code ...

1 year ago | 1

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Why is the FPGA image for UHD different?
>> Does Mathworks allow the FPGA to be modified using the HDL Coder toolset? Yes, if you have an FPGA/SoC on the board you ca...

1 year ago | 0

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how to reduce Estimated Slice LUTs Utilization in FPGA code generation process.
You may find these links helpful to reduce your area consumption on the hardware. https://www.mathworks.com/help/hdlcoder/ug/re...

1 year ago | 1

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Answered
Relationship between FPGA Sample Frequency, FPGA Clock Frequency, Simulink Solver Rate and Oversampling Factor
Simscape to HDL workflow if you are referring to Simscape HDL workflow, attached is a doc that explains the relationship a bit....

1 year ago | 0

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fixing clock frequency and sample time of control system model using hdl coder
See the attached document on the concept of sample time in the model and its relation to clock in the generated code using HDL C...

1 year ago | 0

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errors with Simscape and SSC HDL Coder Workflow Advisor
It looks like this issue fixed in R2024a update4. https://www.mathworks.com/support/bugreports/3262131 Can you consider upgra...

1 year ago | 0

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Answered
Does Simscape Specialized Power Systems blocks work with HDL Coder?
SPS blocks are not currently supported for HDL Code Generation. Please reach out to tech support and share your model of interes...

1 year ago | 0

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errors with Simscape and SSC HDL Coder Workflow Advisor
Happy to diagnose this further. Would you be able share your model with us? Thanks.

1 year ago | 0

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ive been trying to generate vhdl code using hdl code genrator on matlab 2020a but its showing error regarding the use of fi in my code , can someone fix it for me ? thankyou
Please review MATLAB design patterns here. https://www.mathworks.com/matlabcentral/fileexchange/50098-hdlcoder-design-patterns-...

1 year ago | 0

Answered
What is the reason for error in HDL Coder and Cadence Stratus HLS tutorial?
openExample('hdlcoder/GetStartedWithMATLABToSystemCWorkflowUsingHDLCoderAppExample') https://www.mathworks.com/help/hdlcoder/gs...

1 year ago | 0

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HDL Tool setup issue
Step1: First check if Vivado is on your system path in your command window. Find out the location of the vivado from within MA...

1 year ago | 0

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how can I covert my customize MATLAB to HDl code
This page provides some examples and workflows for HDL code generation from MATLAB and Simulink. https://www.mathworks.com/ma...

1 year ago | 0

Answered
OFDM implementation over rayleigh channel with doppler , matlab(simulink) to hdl
These two examples might be helpful. https://www.mathworks.com/help/wireless-hdl/ug/hdlofdmtransmitter.html https://www.mathwo...

1 year ago | 0

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What is the reason for error in HDL Coder and Cadence Stratus HLS tutorial?
We are not aware of such issues with Stratus integration. The error seems to happen post MATLAB to SystemC translation during St...

1 year ago | 0

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Atan2 block native floating point single HDL generation needs more pipelining
Improved performance for Atan2 block in the R2024a release. HDL Coder has enhanced the design implementation of the Atan2 block...

1 year ago | 0

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Answered
How to get Simulink HDL Coder RAM with non power of 2 depth.
Does this solve your usecase? function y = ramBanksScalarInput(u, addr) % addr --> 12bits % u --> uint8 persistent ram...

1 year ago | 0

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Answered
How to get Simulink HDL Coder RAM with non power of 2 depth.
I wonder if you can use the RAM banks feature in HDL Coder. https://www.mathworks.com/help/hdlcoder/ref/hdl.ram-system-object...

1 year ago | 0

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Assertion failed error while convereting simulink model to HDL code
Can you please share your model? This error message is not expected. Thanks.

1 year ago | 0

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Answered
Adaptive pipelining design cannot insert the required number of registers in a feedback loop with integral modules
What version of MATLAB are you using? Can you please share your model? Have you tried using Oversampling factor (>1) to allocat...

1 year ago | 0

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Answered
Failed Generated HDL code, testbench.
The model on the left has root ports; no stimulus/source blocks in the Simulink. The model on the right has valid sources/...

1 year ago | 0

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Examples of Simulink models of spacecraft subsystems controlled by FPGA algorithms
HDL Coder Evaluation Reference Guide https://www.mathworks.com/matlabcentral/fileexchange/58941-hdl-coder-evaluation-referenc...

1 year ago | 1

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Answered
Not able to Build FPGA BitStream for Simscape example model Half Wave Rectifier
Can you reach out to tech support? I am not sure if this could be Vivado version related issue.

1 year ago | 0

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Delay balancing error while using HDL coder
Hi Sanil, would you be able to share your model? Do not hesitate to reach to technical support and we can help further assist y...

1 year ago | 0

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Not able to Build FPGA BitStream for Simscape example model Half Wave Rectifier
https://www.mathworks.com/help/hdlcoder/ug/simscape-hil-speedgoat-fpga-io-modules.html What version of synthesis tools AMD/Xi...

1 year ago | 0

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How to work with arrays in HDL Coder?
See the attached sample code that demonstorates (line 15, 16) on how create large arrays. I am assuming you are using...

1 year ago | 0

Answered
Why I can only choose Xilinx Vivado as the Synthesis tool?
Can you tell us what version of MATLAB are you using? Intel/Altera is supported. You need to have the right support package ins...

1 year ago | 0

Answered
How to give random inputs for my simulink design?
You have to wrap the imported Simulink model from HDL Code into a subsystem. Add sources (constants, toworkspace blocks...) an...

1 year ago | 0

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Convert Simulink to m file
Correction in the above thread / Accepted Ansswer. Simulink Coder and embedded Coder products support C, C++ code generation...

1 year ago | 1

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FPGA Turnkey doesn't update Xilinx Vivado as synthesis tool even after setting tool path
Turnkey workflows are deprecated https://www.mathworks.com/products/hdl-coder.html To target FPGA and SoC devices, use the IP...

1 year ago | 0

Answered
MATLAB Function always infers outputs as doubles
It would be hard to reproduce with the partial information above. Sharing a sample MATLAB function supported syntax for HDL cod...

1 year ago | 0