Answered
Get inverse of scalar in hdl code generation
There are multiple ways to generate HDL from HDL with reciprocal and divide operators. If the scalar variable you are computin...

11 months ago | 0

Answered
IP core generation fails with vivado error
Closing this unanswered thread. This issue is resolved starting R2016a release. Please reach out to tech support if you see th...

11 months ago | 0

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Answered
Generate a PWM in FPGA using a customised carrier.
There are several pulse generator blocks in the Simulink library that are on the HDL Coder roadmap for automatic code generation...

11 months ago | 0

Answered
Dynamic LUT in HDL coder
LUT with BP data as an input is a work in progress feature in HDL Coder. Reach out to tech support for your requirements. Unt...

12 months ago | 0

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Answered
about the Deep Learning HDL Toolbox Support
You can customize and target the DL HDL Toolbox generated code for any FPGA/ASIC/SoC hardware including Xilinx/AMD devices. h...

12 months ago | 0

Answered
fimath error in hdl coder
I am assuming you are using MATLAB code to HDL or MATLAB Function Block in Simulink. Can you share your sample model? Usually f...

12 months ago | 0

Answered
Xilinx ZCU102 not booting with pre-built image
This could be FSBL related error unrelated to HDL Coder. Found several references here. I will try to research a bit more. Pleas...

12 months ago | 0

Answered
Sending waveform specifications from matlab to fpga
Please reach out to tech support or share a sample testbench (that generates the MRI waveform) and design (intended for FPGA) fo...

12 months ago | 0

Answered
How to disable clockdriver logic and clr port (automatic added) in generated vhdl code?
This is an integraiton workflow between HDL Coder from MathWorks along with Xilinx System Generator (XSG) from AMD. https://ww...

12 months ago | 0

Answered
Bug related to using selector block with complex data type in HDL code generation
Can you share your sample model and the release of MATLAB you are encountering this error? Please find the attached model and t...

12 months ago | 0

Answered
Estimate the resource utilization for custom board that has the Kintex7 chip family
This is a known issue and is being actively resolved. It is due to a bug in the format of the device list for Kintex7 family...

1 year ago | 0

Answered
HDL code generation for FFT
If you are looking for MATLAB coding style for generating HDL using HDL Coder you can find some samples here. https://www.mat...

1 year ago | 0

Answered
matlab code for hdl conversion
HDLCoder Design Patterns and Examples This link has several tutorials in this submission show how to generate HDL from MATLAB...

1 year ago | 0

Answered
Native floating-point latency and adding delay block.
You can just model the math and let HDL Coder figure out how to pipeline the design. >> makehdl('dut_nfp/Su...

1 year ago | 1

Answered
Failed Internal Error: Could not connect the blocks in the model during HDL Code generation
This usually indicates the model cannot be put in a compiled state prior to HDL Code generation. You should consider restart...

1 year ago | 0

Answered
How can I connect fpga board basys3ᵀᴹ to Matlab simulink ?
You can use this example as a reference to create a workflow for your Basys Board. https://www.mathworks.com/help/hdlcoder/ug/d...

1 year ago | 0

Answered
How to implement a digital control transfer function on an FPGA using HDL coder?
Have you considered realizemdl function to generate a Simulink and using HDL Coder to generate code from the Simulink model? ...

1 year ago | 0

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whether regressionenseblepredict block can be used in hdl coder?
In general the code you posted cannot be directly be used to generate HDL. You need to break the code into design.m (DUT) an...

1 year ago | 0

Answered
Integrating HDL QPSK Transmitter and Receiver into Xilinx Vivado
HDL QPSK Transmitter and Receiver https://www.mathworks.com/help/comm/ug/hdlqpsktransmitterreceiver.html This example shows ...

1 year ago | 0

Answered
Does MathWorks support the VC707 with HDL Coder & HDL Verifier? If yes, starting at what version of your tools and ending with what version?
HDL Coder supports several evaluation boards out of the box. Virtex-7 VC707 development board is supported out of the box. http...

1 year ago | 1

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Answered
Training data from a read of the input datastore contains invalid bounding boxes
This example is about yolov2 but may have some useful training and deployment tips. https://www.mathworks.com/help/deep-learn...

1 year ago | 0

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Answered
Unable to update models in OFDMTxVerification.m
I am unable to reproduce the issue. Attaching the generated HDL code. >> license inuse matlab >> runOFDMTransmitterMode...

1 year ago | 0

Answered
Unable to update models in OFDMTxVerification.m
>> can give any suggestions or references for beginners to use Simulink for HDL synthesis? https://www.mathworks.com/matlabce...

1 year ago | 0

Answered
How to add TCL script to HDL Coder IP Core generation
In the HDL Workflow Advisor for Generic ASIC/FPGA workflow, in the FPGA Synthesis and Analysis > Create Project task, in the Add...

1 year ago | 0

Answered
The obtained FPGA (Hardware-in-the-loop) output waveform is inconsistent with Simulink simulation results.
Using Simulink / Simscape for modeling and targeting a State space model to FPGA hardware is well established HDL Coder workflow...

1 year ago | 0

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Answered
HDL Coder to / downto order
The control is now available starting R2023b release for boolean arrays. https://www.mathworks.com/help/releases/R2023b/hdlc...

1 year ago | 0

Answered
Can I control the HDL to/downto designation used for arrays during HDL generation?
The control is available starting R2023b release for boolean arrays. https://www.mathworks.com/help/releases/R2023b/hdlcoder...

1 year ago | 0

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Answered
HDL-Coder: Vivado gives errors creating bitstream due to disconnected URAM cascade inputs
>> Using Simulink/HDL Coder, I've created a system that works "just great" Glad to hear it. The error you describe in the mess...

1 year ago | 0

Answered
why matlab throws an error while doing "build model" in soc builder? the error "version 2022.2 of tool xilinx vivado is not supported in hdl workflow advisor. How to fix it?
Each release HDL Coder is tested with specific versions of EDA tools. R2023a release is officially tested with the following v...

1 year ago | 0

Answered
Represent std_logic_vector in Simulink
HDL Coder supports fixed point data types with integer lengths ranging from 1 to 128 bits. During the HDL code generation proce...

1 year ago | 0

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