Answered
Force MATLAB code to run on hardware
Please share your code / model that you want to generate HDL from. if you are taking the ML/DL route, please consider https://w...

6 months ago | 0

Answered
How to create a simulink model for testbench
You need a testbench and HDL DUT subsystem to generate a valid RTL design and testbench from a Simulink model >> makehdl('l...

6 months ago | 0

Answered
Error while generating HDL code from Simulink for Canny Edge Detection
For pure pixel in and pixel out based streaming interface DUT, the blocks such as frame to pixel and pixel to frame should be ou...

6 months ago | 0

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Answered
HDL Coder For Each Subsystem Assertion failed: B:\matlab\src\cgir_hdl\pir_tags\ForEachDataTag.hpp:178:nativeVObj.get()
The error message is not expected. Can you share your model? Either HDL Coder needs to generate code from the model or generate ...

6 months ago | 0

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Answered
How to get the stored integer representation of a single-precision floating point in simulink (HDL Coder)?
https://www.mathworks.com/help/hdlcoder/ref/floattypecast.html Float Typecast Typecast a floating-point type to an unsigned in...

7 months ago | 1

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Answered
wait statement without UNTIL clause not supported for synthesis Error when using HDL coder
Please reach out to tech support if this issue is still reproducible. % Copy the AES demo files to a temporary folder mlhdlc_d...

7 months ago | 0

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Matlab code generation and support for Xilinx Cora Z7-07S
HDL Coder doesn't have explicit support for this board, but the closest board that we support looks to be the ZedBoard or ZC702....

7 months ago | 0

Answered
SystemC code generation directly from SIMULINK model
HDL Coder generates Synthesizable VHDL, Verilog and SystemVerilog for a DUT in Simulink model for targeting ASIC/FPGA/SoC workfl...

7 months ago | 0

Answered
Assertion Error in HDL Coder
This is not an expected error from the product. Can you please provide the reproduction steps with support team? We will try to ...

7 months ago | 0

Answered
Multiple IOSTANDARDs for a single HDL coder interface
https://www.mathworks.com/help/hdlcoder/ref/hdlcoder.board.addexternaliointerface.html addExternalIOInterface('InterfaceID',int...

7 months ago | 1

Answered
Error running simulink with QuestaSim. Failed to connect to server. Make sure loaded HDL simulator library is using shared memory.
It looks like you are generating cosimulation model from HDL Coder. The issues seems related to either installation of the HDL...

8 months ago | 0

Answered
HDL FIFO Reset Problem
Would you be able to share your sample model? You can prune it to just show HDL FIFO block. Found a relevant report here. Need ...

8 months ago | 0

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Error while using vector real gateway in
https://www.xilinx.com/products/design-tools/vitis/vitis-model-composer.html This issue needs to be posted to AMD tech suppor...

9 months ago | 0

Answered
Delay balancing error using R2023b, but have not experienced this in R2017b
The model fails code generation due to pipeline requests at the faster rate that need to be balanced. Need to review generated...

9 months ago | 0

Answered
How do i define an array as a HDL input?
It would be helpful to share your model. HDL Coder supports vector inputs at the DUT interface. Attached is an example of 40poi...

9 months ago | 2

Answered
add_block from other toolboxs
Run this command to see the supported block list. >> hdllib('html') ### HDL supported block list hdlblklist.html ### HDL impl...

9 months ago | 0

Answered
Scalarize Vector Ports option get the HDL code running time is infinite
You have unsynthesizable IO in your model. Please consider IO optimization to convert the frame model to sample model manually o...

9 months ago | 0

Answered
From Simulink to Vivado
Closing the thread. This error is not reproducible since 2019a release. Please reach out to tech support if you see the issue...

9 months ago | 0

Answered
How can i generate a triangular wave form using HDL supported blocks
See the attached sample model (with updown carrier type) you can generate triangular wave. Some examples you may also find ...

9 months ago | 0

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Answered
SIMULINK - HDL code generation with floating point & matlab function block
This restriction is relaxed since R2019b. Simulink Blocks Supported by Using Native Floating Point https://www.mathworks.com/...

9 months ago | 0

Answered
Icc64.exe has stopped working
Please check the supported compilers here https://www.mathworks.com/support/requirements/supported-compilers.html Please note a...

9 months ago | 0

Answered
Get inverse of scalar in hdl code generation
There are multiple ways to generate HDL from HDL with reciprocal and divide operators. If the scalar variable you are computin...

9 months ago | 0

Answered
IP core generation fails with vivado error
Closing this unanswered thread. This issue is resolved starting R2016a release. Please reach out to tech support if you see th...

9 months ago | 0

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Answered
Generate a PWM in FPGA using a customised carrier.
There are several pulse generator blocks in the Simulink library that are on the HDL Coder roadmap for automatic code generation...

9 months ago | 0

Answered
Dynamic LUT in HDL coder
LUT with BP data as an input is a work in progress feature in HDL Coder. Reach out to tech support for your requirements. Unt...

9 months ago | 0

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Answered
about the Deep Learning HDL Toolbox Support
You can customize and target the DL HDL Toolbox generated code for any FPGA/ASIC/SoC hardware including Xilinx/AMD devices. h...

9 months ago | 0

Answered
fimath error in hdl coder
I am assuming you are using MATLAB code to HDL or MATLAB Function Block in Simulink. Can you share your sample model? Usually f...

10 months ago | 0

Answered
Xilinx ZCU102 not booting with pre-built image
This could be FSBL related error unrelated to HDL Coder. Found several references here. I will try to research a bit more. Pleas...

10 months ago | 0

Answered
Sending waveform specifications from matlab to fpga
Please reach out to tech support or share a sample testbench (that generates the MRI waveform) and design (intended for FPGA) fo...

10 months ago | 0

Answered
How to disable clockdriver logic and clr port (automatic added) in generated vhdl code?
This is an integraiton workflow between HDL Coder from MathWorks along with Xilinx System Generator (XSG) from AMD. https://ww...

10 months ago | 0