HDL Verifier™ Support Package for Xilinx® FPGA Boards contains the board definition files for FPGA-in-the-loop (FIL) simulation with HDL Verifier and supported Xilinx FPGA and Zynq® SoC boards. With FIL simulation, use MATLAB® or Simulink® to test designs in real hardware for any existing HDL code.
The FPGA Data Capture capability lets you observe signals from your design in MATLAB while the design is running on the Xilinx FPGA or Zynq SoC. Then use these signals in MATLAB or Simulink for analysis and verification, or view them using the Logic Analyzer in DSP System Toolbox.
The MATLAB as AXI Master IP included in the support package enables you to read from or write to on-board memory locations directly from MATLAB.
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