Due to the down-sampling requirement, the rate transition HDL block is used to sample at a lower rate of the data stream. Also, to pair the outputs in axis stream, muxes are used with serializer1D to format the axis Tdata output. Different rate transition blocks are used to align with the bit signal transition requirement at different ports. The system match the signal route color to show the rates are matched, as shown in Fig. 1.
But the HDL workflow advisor always fail at the IP core generation step with the highlighted sample rate requirement not met, as shown in Fig. 2 although the color format and the rates from these ports are verified to be at the same.
Question is, what causes this rate "inconvergence"? What is the solution for it? Is there any other way of compensating the serializer clock rate changes?