I need to design decimation flter in VHDL so i choose this example of digital down converter.
However parallel architecture of filter in HDL generator after synthesis takes 17k LE in FPGA . In my FPGA i have only 8k LE and 48 multipliers . My question is how to generate serial or partialy serial filter in HDL Generator.
After all steps of the tutorial I tried to use filterDesigner and import my filter from Workspace (and then change properties of HDL generation to serial) but the imported filter looks diffrent form what I designed.
(on the right my CIC-FIR-FIR filter, and on the left imported filter to filterDesigner
Second question. Im confused about clocking frequency of the whole filter block.
In my FPGA board Input signal to the ADC is square 1Khz. Sample rate from ADC is 1MSps(1MHz). Then there is multiplier with sine and cosine 1khz (so the product is desired DC and 2Khz,4khz ,8khz etc unwanted harmonics) . Then there is CIC with Decimation factor 1000, so second stage FIR is 10KHz sampling and 2 decimation factor, then third stage have 5kHz sample rate and also 2 decimation factor (like in GSM DDC example).
What shoud be the value of the clock source (clk) or mayby all three stages should be clocked from three drifferent clocks? Or with HDL parallel filter architecture clock for filters should be the same as ADC sample rate (1MHZ) ?