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For HDL code generation, the float point to fixed point conversion is ok. Because of "Accounting for output port latency: 10 cycles", the test bench does not agree with the HDL code. How to solve this problem?

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For HDL code generation, the float point to fixed point conversion is ok. Because of "Accounting for output port latency: 10 cycles", the test bench does not agree with the HDL code. How to solve this problem?

Accepted Answer

Bharath Venkataraman
Bharath Venkataraman on 31 Oct 2018
The HDL testbench will account for this latency. So generating the HDL code and testbench will let you run the modified testbench with the appropriate latency of 10 cycles.
If you want to balance the delay added in one path to the other, turn Balance Delays option on and the parallel paths will get an additional latency of 10 cycles to match.

  1 Comment

jing xu
jing xu on 2 Nov 2018
Thanks for your help. I code in matlab function form rather than in simulink. when I try to map persistent variable to RAM and the RAM mapping threshold is not satisfied, the data generated by modelsim does agree with the expected data. But when RAM mapping threshold is satisfied and the persistent variable is mapped to RAM , the data generated by modelsim does not agree with the expected data. And the option 'Generate instantiable code for functions is not chosen. Warning information :Delay balancing failed due to an artificial feedback loop.

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More Answers (1)

Bharath Venkataraman
Bharath Venkataraman on 2 Nov 2018
It appears that delay balancing cannot balance the delays added because the added delays are in a feedback loop. If you can share the code, I can get someone to look into it.

  2 Comments

jing xu
jing xu on 2 Nov 2018
N0=1024; N=N0*4; FFT_flag=1>0; Scaling_flag=1<0; x=0:1:N-1; x=x.'; y=exp(1j*2*pi*x*0.2*0); y=randn(N,1)+1j*randn(N,1); d_out_r=zeros(N,1); d_out_i=zeros(N,1); valid_final=zeros(N,1); rst=1>0;
test_bench.m for i=1:N rst=1<0; data_in=y(i); data_in_r=real(data_in); data_in_i=imag(data_in); [data_out_r0,data_out_i0, valid_out]=BF1024_I(data_in_r,data_in_i,FFT_flag);
d_out_r(i)=data_out_r0;
d_out_i(i)=data_out_i0;
valid_final(i)=valid_out;
end
jing xu
jing xu on 2 Nov 2018
function [data_out_r,data_out_i, valid_out]=BF1024_I(data_in_r,data_in_i,FFT_flag) data_in=complex(data_in_r,data_in_i); % if rst==1 % clear all; % end persistent counter; persistent flag; persistent D_Buff; persistent Ser ctr_r ctr_w;
C=complex(0,0); D=C;
N0=1024; %% 蝶形涉及的数据深度; % N N1=N0/2; %% N1=N0/2 1/2 % AD0=1:1:N1-1; % AD1=2:1:N1; N2=N0*3/4; %% 3/4
if isempty(Ser) Ser=complex(zeros(N1,1),zeros(N1,1)); ctr_r=uint16(2); ctr_w=uint16(1); end
if isempty(counter) % buff1=complex(zeros(N1,1),zeros(N1,1)); D_Buff=complex(0,0); flag=0; counter=uint16(0); end s=D_Buff;
data_out_temp=Ser(ctr_r); Ser(ctr_w)=s;
if counter<N1 %% 延时寄存器加了一个延时;1/2 8 %% 数据未到全,先进行缓存; if flag==1 %% 第二帧数据才有用
data_out=data_out_temp;
data_out_r=real(data_out);
data_out_i=imag(data_out);
valid_out=1;
else %%刚开始的第一帧数据时,没有有效数据输出;
data_out=complex(0,0);
valid_out=0;
data_out_r=real(data_out);
data_out_i=imag(data_out);
end
else
C=data_out_temp+data_in;
D=data_out_temp-data_in;
%%输出给BF16_II
data_out=C;
data_out_r=real(data_out);
data_out_i=imag(data_out);
valid_out=1;
%%减的输出到移位寄存器;
if counter>=N2
if FFT_flag==1 %%乘以-j;
D=complex( imag(D),-real(D));
else %%%%乘以j;
D=-complex( imag(D),-real(D));
end
end
end
%% 准备好写得数据; if counter<N1 %% 新到的数据与本地生成的数据都需要延时一个cycle D_Buff=data_in; %% write else D_Buff=D; %% write end
if ctr_r==N1 ctr_r=uint16(1); else ctr_r = ctr_r + uint16(1); end
if ctr_w == N1 ctr_w = uint16(1); else ctr_w = ctr_w + uint16(1); end
if counter<(N0-1) counter=counter+uint16(1); elseif (counter==(N0-1)) counter=uint16(0); flag=1; end
end

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