Autogenerated VHDL for FPGA - In - The Loop DUT I/O Issue "** HDL Parser Error: line XX: near "vector_of​_std_logic​_vector32"​, found unsupported data-type "vector_of​_std_logic​_vector32"​"

I have a Simulink model with rather complicated (and numerous) inputs and outputs. The current set up groups these connectors together in a nice logical way. When I generate the HDL code, MATLAB creates a package type that brings much of this neatness to the HDL code itself. In the package file, there is

TYPE vector_of_std_logic_vector32 IS ARRAY (NATURAL RANGE href = ""</a>) OF std_logic_vector(31 DOWNTO 0);

And one of the corresponding input ports is

my_input : IN vector_of_std_logic_vector32(0 TO 6);

However, when I run the FIL wizard, I get these messages reported by the HDL parser:

HDL Parser Error: line XX: near "vector_of_std_logic_vector32", found unsupported data-type "vector_of_std_logic_vector32"

And I cannot generate the FIL System block.

I found in the FIL documentation that the only supported I/O types are std_logic and std_logic_vector. Is there a workaround to use these _pkg type defined I/O? Otherwise, if I enable "Scalarize vector ports," I can generate an FIL block, but it now has hundreds of inputs. I can make a wrapper for it, but I'm wondering if there's a way I can natively handle these more intricate I/Os.

[mar gian]

did you manage to find it ?

I am dealing the same issue.

Answer 1

[Priyanka]

In HDL coder setting enable Scalarize ports.

Steps for enabling Scalarize ports:

HDL code --> Setting --> Configuration parameter window will open --> Under configuration parameter (in left panel) --> HDL code generation --> Global setting --> Ports --> Scalarize ports - turn ON