Issues: FIR filter by HDL Coder on Redpitaya platform

My goal is to implement a modulation on FPGA hardware(Red Pitaya). So i tried some basic applications like sine generator and FIR filter using Matlab HDL Coder. The sine generator works fine, but the FIR filter (generated with filterDesigner) doesn't operate as wanted. The design you can see in the appendix, the initialization in Xilinx Vivado was:

FIR_filter (.clk(adc_clk), .reset(1'b0), .clk_enable(1'b1), .In(data_adc), .ce_out(), .Out(data_dac));

As you can see the filter quantization for input and output is set to 14-bit signed - fitting to adc/dac specification.

Now, although the input is in idle, the output signal is incorrect. There is an random shot of that noise appended.

Is that a problem of quantization, data type or data overflow? So what would be the correct setting?

Or are there other basic condition to take care at direct implementation with Verilog Code by Matlab HDL Coder?

That's the project: GitHub: FIR_Filter

Answer 1

[Kiran Kintali]

>> mlhdlc_demo_setup('sfir')