HDL Code Verification and Debugging with MATLAB and Simulink

Day 1 of 2

Verification and Debugging Workflows for FPGA and ASIC Design

Objective: Gain an overview of the verification and debugging workflows using MathWorks tools.

• Review the importance of a robust testbench.
• Explore workflows for verifying both generated and handwritten HDL code.
• Learn about hardware debugging and prototyping options.
• Install required Add-ons and Hardware Support Packages.

Testbench Generation

Objective: Introduce advanced techniques for thorough HDL verification using model-based design, simulation, code coverage, and automated testbench generation.

• Develop test stimuli based on the test plan, leveraging model coverage to ensure thoroughness.
• Perform verification of generated HDL code with an HDL simulator and a generated testbench.
• Use code coverage to identify untested portions of the code and improve test completeness.
• Verify generated HDL code in Simulink through co-simulation.
• Automatically generate a SystemVerilog DPI testbench from the full Simulink model and execute it for verification.

Co-Simulation

Objective: Verify and analyze HDL code by integrating MATLAB and Simulink into co-simulation workflows, enabling combined simulation of HDL and Simulink models.

• Verify existing HDL code using MATLAB and Simulink through co-simulation.
• Integrate co-simulation models into simulation-based test environments with Simulink Test.
• Call MATLAB functions directly from an HDL simulator.
• Simulate HDL code alongside Simulink blocks using co-simulation blocks.

Day 2 of 2

FPGA-in-the-Loop

Objective: Prepare the necessary tools for verifying designs on an FPGA board. Use FPGA-in-the-Loop to validate implemented designs, whether they originate from generated or manually written HDL code.

• Identify appropriate use cases for FPGA-in-the-Loop (FIL) simulation.
• Set up hardware and software environments for FIL.
• Use HDL Workflow Advisor to perform FIL verification for auto-generated HDL code.
• Create a FIL block using the FIL Wizard and use it in MATLAB or Simulink.
• Accelerate FIL simulation time with frame-processing.
• Compare the design running on the board with a “golden reference model”.

FPGA Data Capture

Objective: Capture live data from a running FPGA design to view and debug internal signals. Import the captured data into MATLAB or Simulink for comprehensive debugging and analysis.

• Integrate data capture capabilities into HDL IP and deploy it to FPGA hardware.
• Capture and analyze live data from FPGA boards using the FPGA Data Capture App.
• Configure trigger and capture conditions to optimize data acquisition.
• Automate the FPGA data capture workflow using MATLAB.
• Generate and configure FPGA Data Capture IP cores for existing HDL designs.
• Use the FPGA Data Reader block in Simulink to collect and visualize data from FPGAs.

Accessing AXI Registers on FPGA Using MATLAB and Simulink

Objective: Access on-chip memory locations on an FPGA from MATLAB or Simulink using AXI Manager to perform read and write operations.

• Access FPGA on-chip memory locations from MATLAB or Simulink using AXI Manager for reading and writing.
• Distinguish between AXI Manager and AXI Subordinate roles and their applications.
• Create and deploy an AXI Manager IP core within an FPGA design.
• Use the AXI Manager object in MATLAB to perform read and write operations on FPGA on-chip memory.