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Modeling External Memory

You can model external memory using features from Vision HDL Toolbox™ Support Package for Xilinx® Zynq®-Based Hardware or SoC Blockset™. Both products provide models for a frame buffer or a random access interface. They both also map your subsystem ports to physical AXI memory interfaces when you generate HDL code and target a prototype board.

Vision HDL Toolbox Support Package for Xilinx Zynq-Based Hardware provides a simple model of the memory interface. It does not model the timing of the interface. This level of modeling assists with targeting a memory interface on hardware, but behavior can differ between the simulation and the hardware. For more information, see Model External Memory Interfaces (Vision HDL Toolbox Support Package for Xilinx Zynq-Based Hardware).

SoC Blockset provides library blocks to model a memory controller and multiple memory channels. This model calculates and visualizes memory bandwidth, burst counts, and transaction latencies in simulation. You can also model memory accesses from a processor as part of hardware-software co-design. Use the SoC Builder app to generate code for FPGA and processor designs and load and run the design on a board. You can also deploy an AXI memory interconnect monitor on your FPGA, which can return memory transaction information for debugging and visualization in Simulink®. This level of modeling helps you verify throughput and latency requirements and enables modeling of multiple memory consumers, including processor memory access. For more information, see Memory Transactions (SoC Blockset).

Frame Buffer

Vision HDL Toolbox Support Package for Xilinx Zynq-Based Hardware SoC Blockset

This figure shows part of the Histogram Equalization with Zynq-Based Hardware (Vision HDL Toolbox Support Package for Xilinx Zynq-Based Hardware) example. The Video Frame Buffer block accepts and returns the pixel streaming interface used by Vision HDL Toolbox blocks. It reads and returns an entire frame when you set the pop signal to 1. To use this block in your designs, copy it from the example model.

This figure shows part of the Histogram Equalization Using Video Frame Buffer (SoC Blockset) example. The example shows how to use the Memory Channel and Memory Controller library blocks to model a frame buffer and additional memory consumers. You can use this model to confirm that the memory interface meets the throughput and latency requirements of your design. You can measure the bandwidth and transaction latency for each memory consumer and check the measurements against the total bandwidth available from the memory. To model a frame buffer that supports the pixel streaming interface used by Vision HDL Toolbox blocks, configure the Channel type parameter of the Memory Channel block as AXI4 Stream Video Frame Buffer.

Random Access

Vision HDL Toolbox Support Package for Xilinx Zynq-Based Hardware SoC Blockset

This figure shows part of the Image Rotation with Zynq-Based Hardware (Vision HDL Toolbox Support Package for Xilinx Zynq-Based Hardware) example. The External Memory block reads and writes to any address in the memory. In this case, rather than connecting the pixel stream to the memory interface, your custom FPGA logic must generate read and write transactions with specific addresses. To use this block in your designs, copy it from the example model.

This figure shows part of the Random Access of External Memory (SoC Blockset) example. This design uses a Memory Controller and two Memory Channel blocks to implement a random-access interface. In this case, rather than connecting the pixel stream to the memory interface, your custom FPGA logic must generate read and write transactions with specific addresses.

See Also

(SoC Blockset) | (Vision HDL Toolbox Support Package for Xilinx Zynq-Based Hardware)