Debug SDR Designs Using FPGA Data Capture
This example shows how to debug the HDL IP core of an SDR design generated in the Communications Toolbox™ Support Package for Xilinx® Zynq®-Based Radio by using the FPGA Data Capture (HDL Verifier Support Package for Xilinx FPGA Boards) app from the HDL Verifier™ Support Package for Xilinx FPGA Boards.
HDL Coder Support Package for Xilinx Zynq Platform
Embedded Coder Support Package for Xilinx Zynq Platform
Communications Toolbox Support Package for Xilinx Zynq-Based Radio (this package)
HDL Verifier Support Package for Xilinx FPGA Boards
(Optional) DSP System Toolbox
You can debug the HDL IP core generated for an SDR design by monitoring the IP core internal signals when the IP core is running on real hardware. This example shows how to use the FPGA Data Capture app to capture such signals into MATLAB for debugging analysis. The examples demonstrates this workflow by using the HW/SW Co-Design Implementation of ADS-B Receiver Using Analog Devices AD9361/AD9364 as a reference design.
If you have not already done so, complete the Installation for Hardware-Software Co-Design. In addition, you need to connect the host computer and the development board with a JTAG cable.
Hardware Generation Model
The ADS-B model captures data from the FPGA and receives ADS-B transmissions either from the air or from a previously recorded Mode-S signal transmitted locally using the embedded transmit waveform.
1. Open the ADSB-Model.
2. Mark the signals that need to be analyzed through data capture as test points. To mark a signal as test point, right-click the signal and go to properties. On the Signal Properties block mask, on the Logging and accessibility tab, select the Test point checkbox.
3. In the HDL_ADSB subsystem, open the HDLRxIpCore subsystem. Inside the Compute CRC and Frame validation block, mark the output signals Rxvalid_out and RxData_out as test points. When these signals are marked as test points, they are represented with indicators. These indicators are highlighted with blue circles in the screen cap.
4. Add test points for the signals you are interested in. In this example, RxData_out and Rxvalid_out are marked as test points.
Generate HDL IP Core with Data Capture
The procedure for launching the HDL Workflow Advisor and targeting workflow is similar to the procedure used in the HW/SW co-design workflow. For more details, see the HW/SW Co-Design Implementation of ADS-B Receiver Using Analog Devices AD9361/AD9364 example.
1. Launch the Workflow Advisor.
2. Follow steps 1.1 to 1.2 of the IP Core Generation Workflow of the HW/SW Co-Design Implementation of ADS-B Receiver Using Analog Devices AD9361/AD9364.
3. At Workflow Advisor Step 1.3, select Enable HDL DUT port generation for test points, this enables the display of test points in Target platform interface table. Choose the FPGA Data Capture - JTAG as the Target Platform Interface.
4. In Workflow Advisor Step 3.2, select 1024 as the FPGA data capture buffer size from the drop-down list.
5. Follow the steps 1.4 from IP Core Generation Workflow to step 4.4 Bitstream generation and loading of HW/SW Co-Design Implementation of ADS-B Receiver Using Analog Devices AD9361/AD9364 example.
Capture and Display Data from IP Core
1. To capture data from the Zynq board, you must run the software interface model. Follow the instructions of Running the Software and Hardware on the Zynq board in HW/SW Co-Design Implementation of ADS-B Receiver Using Analog Devices AD9361/AD9364 example to run the software interface model.
2. Open the FPGA Data Capture app by using the command:
3. In the FPGA Data Capture UI, on the Trigger tab, add the tp_Rxvalid_out as a signal with value Rising edge. Change the trigger from Immediately to On trigger. Set the number of capture Windows to 8. Click Capture Data.
4. Once the trigger is satisfied, the tool captures the data and makes it available in the MATLAB workspace.
5. If you have DSP System Toolbox installed, you can use the Logic Analyzer to display the captured data as signal waveforms.
This example shows how to mark signals as test points in an SDR design and how to generate a corresponding HDL IP core for debugging purposes. The example uses the FPGA Data Capture app to capture data from the specified test points.