To open the SoC Model
Creator tool, enter the
socModelCreator command at the
MATLAB® command prompt. In the window that opens, select the reference design and
type of model, set the reference design parameters, customize the design with
preconfigured analog-to-digital converter (ADC) and digital-to-analog converter (DAC)
channels, and optionally add multiple external input/output (I/O) interfaces and AXI
In the Reference Design General section, select the reference design board, reference design name, and supported Vivado® version.
Reference design board — Select the target
hardware board for your reference design. By default, this parameter is set
Xilinx Zynq UltraScale+ RFSoC ZCU111 Evaluation
Kit. This workflow supports the Xilinx®
UltraScale+™ RFSoC ZCU111 evaluation kit and the Xilinx
UltraScale+ RFSoC ZCU216 evaluation kit.
Reference design name — Select the reference
design for which you want to create an SoC model. By default, this parameter
is set to
Real ADC/DAC Interface. Available
options for this parameter vary as per the selected hardware board.
Real ADC/DAC Interface —
Select this option when your design receives and transmits real
Real ADC/DAC Interface with PL-DDR4
— Select this option when your design receives and
transmits real data, and uses DDR4 buffering. Selecting this
option adds an AXI4 interface to your device under test (DUT)
for connection to the DDR4 memory.
IQ ADC/DAC Interface —
Select this option when your design receives and transmits
complex in-phase/quadrature (I/Q) data.
IQ ADC/DAC Interface with PL-DDR4
— Select this option when your design receives and
transmits complex I/Q data and uses DDR4 buffering. Selecting
this option adds an AXI4 interface to your DUT for connection to
the DDR4 memory.
Supported Vivado version — This parameter is read-only and displays the supported Xilinx Vivado version.
This workflow supports Xilinx Vivado version 2020.2 only.
Set the synthesis tool path to point to an installed Vivado Design Suite 2020.2 batch file by entering this command at the MATLAB command prompt. When you execute this command, use your own Xilinx Vivado installation path.
hdlsetuptoolpath('ToolName','Xilinx Vivado','ToolPath', ... 'C:\Xilinx\Vivado\2020.2\bin\vivado.bat');
In the Model Creation section, specify the name and select the type of your model.
Top model name — Specify the name of the
top model (in SLX format) that you want to create. By default, this
parameter is set to
Create models representing — Select the type of the SoC model that you want to create. The SoC model can be of these types.
FPGA and processor (default) — Include an FPGA model, processor model, and the register channel into your top model.
FPGA and memory — Include an FPGA model and a memory system with a memory controller and memory channels into your top model.
FPGA only — Include an FPGA model into your top model.
The Reference Design Parameters section lists the parameters that are available with the selected reference design. Available options for these parameters vary as per the hardware board and reference design that you select in the Reference Design General section.
Select the AXI4-Stream DMA data width parameter as
Specify the ADC sampling rate (MHz) and DAC sampling rate (MHz) parameters as scalars in a range that depends on the selected hardware board.
Select the ADC decimation mode (xN) parameter as the required decimation factor value and the DAC interpolation mode (xN) parameter as the required interpolation factor value.
Select the ADC samples per clock cycle and DAC samples per clock cycle parameters as the required number of ADC and DAC samples per clock cycle, respectively.
Select the ADC mixer type and DAC mixer
type parameters as
Available options for these parameters vary as per the selected reference
Specify the frequency of the numerically-controlled oscillator (NCO) mixer for an ADC and DAC channel by using the ADC/DAC NCO mixer LO (GHz) parameter.
Select the Enable multi-tile sync parameter as
true to enable multi-tile synchronization
(MTS). Enabling MTS has additional requirements. For more information on MTS
mode, see Zynq UltraScale+ RFSoC RF Data Converter v2.3 in the Xilinx documentation.
Do not change the values of the Tile clock output frequency (MHz) and DUT synthesis frequency (MHz) parameters. These values are prepopulated. The Tile clock output frequency (MHz) parameter shows the output clock frequency of the ADC and DAC tile, and the DUT synthesis frequency (MHz) parameter shows the synthesis frequency of the DUT.
Select the phase-locked loop (PLL) reference clock in MHz by using the PLL reference clock (MHz) parameter.
Select the Connect to AXI4-Master DDR4 MIG parameter
true to connect the model to DDR4 memory.
Available options for this parameter vary as per the selected reference
The number of samples per clock cycle, or DMA data width, affect the data type of the signal lines to reflect the word length. For example, when you select 4 samples per clock cycle, the word length for the ADC or DAC I/O lines is 64 bits because each sample is 16 bits.
In the Internal Interfaces section, you can customize the reference design with preconfigured DAC and ADC channels. The number of DAC and ADC tiles and the number of channels in each tile depend on the selected hardware board. For example, if you select the Xilinx Zynq UltraScale+ RFSoC ZCU111 evaluation kit, the DAC pane contains two tiles (Tile 0 and Tile 1), and each tile contains four DAC channels. The ADC pane contains four tiles (Tile 0, Tile 1, Tile 2, and Tile 3), and each tile contains two ADC channels. The tiles and DAC or ADC channels indicate the corresponding tiles and DAC or ADC interfaces on the selected hardware board.
In the External IO Interfaces section, select the external I/O interfaces for your model from the available list of interfaces. These external I/O interfaces are board-specific and defined in the board definition file.
In the AXI Registers section, you can add a new AXI register to your model by clicking New. Define the name, direction, data type, and dimension for the newly added register.
Name — Specify the name of the register.
Direction — Select the direction for the
Data type — Select the data type for the
fixdt(1,16,2^0,0), or specify your own data
Dimension — Specify the dimension of the register as a numeric scalar.
You can rearrange the register rows by clicking Move Up and Move Down. Select the row that you want to move up or move down, and then click Move Up or Move Down. To delete any register, select the register that you want to delete and click Delete.
Click Create. A created SoC model opens in a Simulink® window. The SoC model maps the input and output ports to the various ADC and DAC tiles that are associated with the RFSoC device. You can add your algorithm in the subsystem in the created model for simulation, HDL code generation, and SoC deployment.
After you create an SoC model for a specified reference design board, do not change the target hardware board. Even if you change the target board after you create an SoC model, the SoC Builder tool still generates HDL code for the target board for which you have created the model. To change the target hardware board, create a new SoC model for a required reference design board by using the SoC Model Creator tool.
Edit the created model to include the required algorithm. Navigate to the blocks marked FPGA Algorithm in the FPGA model or Processor Algorithm in the processor model. Replace these blocks with your own algorithm model. Then, simulate the system and use the SoC Builder tool to generate and load a bitstream to the FPGA, program the processor, and run the RFSoC application.