Write data to AXI4 memory-mapped slaves
writes all words specified in
data, starting from the address specified
addr and then incrementing the address for each word. The address,
addr, must refer to an AXI slave memory location controlled by the
AXI master IP on your FPGA board. The AXI master object,
the connection between MATLAB® and the AXI master IP.
Access Memory on FPGA Board from MATLAB
Before you can use this example, you must have a design running on an FPGA board connected to the MATLAB host machine. The FPGA design must include an AXI master IP that is customized for your FPGA vendor. The support package installation includes this IP. To include the IP in your project, see the Access FPGA Memory Using JTAG-Based MATLAB AXI Master example.
Create an AXI master object. The object connects MATLAB with the FPGA board and confirms that the IP is present.
mem = aximaster('Xilinx')
mem = aximaster with properties: Vendor: 'Xilinx' JTAGCableName: 'auto'
Write 10 addresses and then read data from a single location. By default, these functions auto-increment the address for each word of data.
writememory(mem,140,[10:19]) rd_d = readmemory(mem,140,1)
rd_d = uint32 10
Read data from 10 locations.
rd_d = readmemory(mem,140,10)
rd_d = 1×10 uint32 row vector 10 11 12 13 14 15 16 17 18 19
Read data 10 times from the same address by specifying that the AXI master read all data from the same address (disabling auto-incrementation).
rd_d = readmemory(mem,140,10,'BurstType','Fixed')
rd_d = 1×10 uint32 row vector 10 10 10 10 10 10 10 10 10 10
Write data 10 times to the same address. In this case, the final value stored in address
writememory(mem,140,[20:29],'BurstType','Fixed') rd_d = readmemory(mem,140,10)
rd_d = 1×10 uint32 row vector 29 11 12 13 14 15 16 17 18 19
Specify the address as a hexadecimal value. Specify for the function to cast the read
data to a data type other than
writememory(mem,0x1c,[0:4:64]) rd_d = readmemory(mem,0x1c,16,'OutputDataType',numerictype(0,6,4))
rd_d = Columns 1 through 10 0 0.2500 0.5000 0.7500 1.0000 1.2500 1.5000 1.7500 2.0000 2.2500 Columns 11 through 16 2.5000 2.7500 3.0000 3.2500 3.5000 3.7500 DataTypeMode: Fixed-point: binary point scaling Signedness: Unsigned WordLength: 6 FractionLength: 4
When you no longer need to access the board, release the JTAG connection.
mem — Connection to AXI master IP on FPGA board
Connection to the AXI master IP on your FPGA board, specified as an
addr — Starting address for write operation
nonnegative integer multiple of 4 | nonnegative hexadecimal value multiple of 4
Starting address for the write operation, specified as a nonnegative integer
multiple of 4 or hexadecimal value multiple of 4. The function casts the address to the
uint64 data type, according to the AXI
master IP address width. The address must refer to an AXI slave memory location
controlled by the AXI master IP on your FPGA board.
If the AXI master IP data width is 32 bits, the memory is 4 bytes aligned, and addresses have 4-byte increments (
0x8). In this case,
0x1is an illegal address and emits an error.
If the AXI master IP data width is 64 bits, the memory is 8 bytes aligned, and addresses have 8-byte increments (
0x10). In this case,
0x4are illegal and emit errors.
If the AXI master IP data width is 32 bits and you set the
'Increment', the address has 4-byte increments.
If the AXI master IP data width is 64 bits and you set the
'Increment', the address has 8-byte increments.
Do not use a 64-bit AXI master for accessing 32-bit registers.
64, specifies a starting address of
data — Data words to write
scalar | vector
Data words to write, specified as a scalar or vector. By default, the function
writes the data to a contiguous address block, incrementing the address for each
operation. To disable address incrementation and write each data value to the same
location, set the
'BurstType' argument to
Before sending the write request to the FPGA, the function casts the input data to
int64 data type. The type conversion follows these rules:
If the input data is
double, then the data is cast to
int64, depending on the AXI master IP data width.
If the input data is
single, then the data is cast to
uint64, depending on the AXI master IP data width.
If the bit width of the input data type is less than the AXI master IP data width, then the data is sign-extended to the width of the AXI master IP data width.
If the bit width of the input data type is greater than the AXI master IP data width, then the data is cast to
uint64. The data is cast to match the AXI master IP data width and the signedness of the original data type.
If the input data is a fixed-point data type, then the function writes the stored integer value of the data.
When you specify a large operation size, such as writing a block of DDR memory, the function automatically breaks the operation into multiple bursts, using the maximum supported burst size of 256 words.
[1:100] specifies 100 contiguous memory
comma-separated pairs of
the argument name and
Value is the corresponding value.
Name must appear inside quotes. You can specify several name and value
pair arguments in any order as
'BurstType','Fixed'directs the AXI master to write all data to the same address.
BurstType — AXI4 burst type
'Increment' (default) |
AXI4 burst type, specified as one of these options:
'Increment'— The AXI master writes a vector of data to contiguous memory spaces, starting with the specified address.
'Fixed'— The AXI master writes all data to the same address.