Access on-board memory locations from MATLAB by using the MATLAB AXI Master IP in your FPGA
design and the
The object connects to the IP over a JTAG, Ethernet, or a PCIe interface and
enables read and write commands to slave memory locations from the MATLAB
|Add AXI master IP path to Vivado project|
|Read data out of AXI4 memory-mapped slaves|
|Write data to AXI4 memory-mapped slaves|
|Release JTAG or Ethernet cable resource|
|Copy board-specific SD card image files to host SD card location|
|Load board-specific SD card image files to target SoC device SD card location|
|Load custom FPGA bitstream and its corresponding DTB file to target SoC device|
|Read and write memory locations on FPGA board from MATLAB|
High-level steps for accessing memory-mapped locations on an FPGA board from MATLAB or Simulink®.
Integrate and configure Ethernet MATLAB as AXI Master.
Configure Ethernet MATLAB as AXI Master for Xilinx Zynq SoC devices.
Integrate and configure MATLAB as AXI Master IP over PCI Express.
Access memory-mapped locations on an FPGA board from Simulink.
Simulate MATLAB as AXI Master using the Vivado simulator.