Documentation

HDL Verifier Support Package for Xilinx FPGA Boards

Debug and test HDL code on Xilinx FPGAs and Zynq SoCs

HDL Verifier™ Support Package for Xilinx® FPGA Boards contains the board definition files for FPGA-in-the-loop (FIL) simulation with HDL Verifier™ and supported Xilinx FPGA and Zynq® SoC boards. With FIL simulation, use MATLAB® or Simulink® to test designs in real hardware for any existing HDL code. FPGA data capture support lets you observe signals from your design in MATLAB while the design is running on the Xilinx FPGA or Zynq SoC. With MATLAB AXI Master IP, you can read from or write to on-board memory locations using MATLAB.

Setup and Configuration

Install hardware support, update firmware, configure hardware connection

FPGA-in-the-Loop Simulation

Verification with FPGA hardware

FPGA Data Capture

Capture signal data from live FPGA

MATLAB AXI Master

Access AXI slave memory on FPGA board from MATLAB