Simulink® Design Verifier™ design error detection analysis detects out of bound array access errors in your model. In simulation, when your model attempts to access an array element using an invalid index, an out of bound array access error occurs.
To detect out of bound array access errors in your model:
On the Design Verifier tab, in the Mode section, select Design Error Detection.
Click Error Detection Settings.
In the Configuration Parameters dialog box, in Design Error Detection pane, select Out of bound array access.
Click Detect Design Errors.
The Simulink Design Verifier log window opens, showing the progress of the analysis.
When the analysis is complete:
The software highlights the model with the analysis results.
The Simulink Design Verifier Results dialog box opens and displays an analysis summary.
If a model contains out of bound array access error, after the first occurrence of array access, Simulink Design Verifier assumes that the array index is within bounds for the remaining analysis. Hence, design error detection objectives that are analyzed after this assumption may be reported as valid, even if the design errors occur in the model.
This example shows how to detect out of bound array access errors and review the analysis results. In the
sldvdemo_array_bounds example model, the ComputeIndex MATLAB Function block uses the input signal values to determine range of indices with minimum
minIdx and maximum
maxIdx. The ArrayOp_Matlab, ArrayOp_MAL, and ArrayOp_SF blocks use the set of integer indices between
maxIdx to access array elements and perform array operations.
Step 1: Open the Model
At the command prompt, enter:
Step 2: Perform Design Error Detection Analysis
The analysis options in the model are preconfigured for out of bound array access error detection. To view these options, in the Simulink Editor, double-click the View Options button.
To perform design error detection analysis, in the Simulink Editor, double-click the Run button. The Simulink® Design Verifier™ Results Summary window opens that displays the progress of the analysis. When the analysis completes, the example model is highlighted with the analysis results.
Step 3: Review Analysis Results
To view the analysis results inside the chart, double-click the ArrayOp_SF Chart block that is highlighted in red.
Simulink Design Verifier detects that the index out of bound errors occurs in array
u in state Diff.
Step 4: Create Harness and Simulate Test Cases
Click the first View test case link. Simulink Design Verifier creates and opens a harness model that contains test cases, that demonstrate out of bound array access errors. In the Signal Builder dialog box, click Start simulation to simulate the harness model with Test Case 2.
The simulation stops before entering the state Diff. The Stateflow® Debugger opens. The following error is shown:
Attempted to access index 4 of u with smaller dimension sizes. The valid index range is 0 to 3. This error will stop the simulation. State 'Diff' in Chart 'sldvdemo_array_bounds_harness/Test Unit (copied from sldvdemo_array_bounds)/ArrayOp_SF': y = u[maxIdx] - u[minIdx];
Keep the Stateflow® Debugger open at this breakpoint. In the
sldvdemo_array_bounds_harness model, hold your cursor over the Diff state to see the data values at this simulation breakpoint.
Using Test Case 2 input signal values, the ComputeIndex MATLAB Function block determines the range of array indices to be 1:4. One-based indexing is consistent with MATLAB syntax, so these indices are valid for the ArrayOp_Matlab MATLAB Function block and the ArrayOp_MAL Stateflow® chart.
The ArrayOp_SF Stateflow® chart uses C as the action language, which does not support one-based indexing. Thus, 1:4 is not a valid index range for array access in the chart. The valid index range for array access in the chart is 0:3, as reported by the error message. When either maxIdx or minIdx evaluates to 4, an out of bound array access error occurs in the ArrayOp_SF Chart block. For more information on zero-based indexing support, see Differences Between MATLAB and C as Action Language Syntax (Stateflow).
Design error detection does not support indexing by
your model attempts to access an array using an index value that evaluates to
Inf, design error detection does not report an out of
bound array access error, but in simulation, an out of bound array access error
Out of bound array access design error detection does not support Index Vector blocks with scalar data inputs. If your model includes an Index Vector block that specifies a scalar data input instead of a vector data input and the control input causes an out of bounds array access, design error detection does not report an error, but an error occurs in simulation.