This example shows how to detect integer overflow errors in a model by using design error detection analysis. Simulink® Design Verifier™ identifies the model constructs that may result in integer overflows and then either proves that the integer overflow cannot occur during simulation or generates test cases that demonstrates the integer overflow error.
In this example, you will perform design error detection analysis on a model, then generate a report that shows which integer overflow objectives were valid and which objectives resulted in errors.
At the command prompt, enter:
The model is preconfigured with the Integer overflow option enabled in the Configuration Parameters dialog box, on the Design Verifier > Design Error Detection pane.
On the Design Verifier tab, click Detect Design Errors.
The software analyzes the model for integer overflow errors. After the analysis completes, the Results Summary window reports that five objectives are valid and two objectives are falsified.
To highlight the analysis results on the model, in the Results Summary window, click Highlight analysis results on model. The valid objectives are highlighted in green and the falsified objectives are highlighted in red.
Controller subsystem. Click the Sum block that is highlighted in red. The Results Inspector window displays the integer overflow objectives.
To view the test case that results in the error, click View test case. The harness model opens and the Signal Builder block displays the test case that results in the error.
For both the Sum blocks that generated the integer overflow, enable the Saturate on integer overflow option. Alternatively, you can double-click the Toggle Saturation on overflow button in the Simulink Editor.
To confirm that the integer overflow error was resolved, on the Design Verifier tab, click Detect Design Errors. After the analysis completes, the software reports that all the objectives are valid.