Simulink® Design Verifier™ analyzes a model to achieve full model coverage. You can use existing test cases or existing coverage data to achieve full model coverage.
Use the Test Generation Advisor to guide model and component analysis.
Specify options that control how Simulink Design Verifier generates tests for the models it analyzes.
Overview of the Simulink Design Verifier options in the Configuration Parameters dialog box.
Review analysis results in the Simulink Design Verifier Results Summary window.
Outlines a process for generating test cases for generated code.
This example shows how to use Simulink® Design Verifier™ to generate test cases to obtain complete code coverage.
This example shows how to compile an S-Function to be compatible with Simulink® Design Verifier™ for test case generation.
Describes limitations and considerations of S-functions and Generated Code in Simulink Design Verifier.
Explains when to extend existing test cases to create a complete test suite.
Extends existing test cases to analyze a model that uses temporal logic.
Extends existing test cases to analyze a closed-loop system in a model.
Extends existing test cases for a model that you have previously analyzed and then modified.
This example shows how to use Simulink® Design Verifier™ functions to log input signals, create a harness model, generate test cases for missing coverage, merge harness models, and execute test cases.
This example shows how to use Simulink® Design Verifier™ to extend an existing test suite to obtain missing model coverage.
This example shows how Simulink® Design Verifier™ can extend test cases with additional time steps to efficiently generate complete test suites.
This example shows how to achieve missing coverage by extending existing test cases after applying parameter configurations.
Explains how to convert subsystems to Model blocks before attempting to achieve missing coverage.
Achieves missing coverage data in a referenced model and combines it with coverage data for the top-level model.
Achieves missing coverage data in a closed-loop simulation model.
This example shows how Simulink® Design Verifier™ can target its analysis to a single subsystem within a continuous-time closed-loop simulation and generate test cases for missing coverage in that subsystem.