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Check Static Range

Check that signal falls inside fixed range of amplitudes

  • Library:
  • Simulink / Model Verification

    HDL Coder / Model Verification

  • Check Static Range block

Description

The Check Static Range block checks that each element of the input signal falls inside the same range of amplitudes at each time step. The Upper bound and Lower bound parameters define the upper and lower bounds of the range. The block then executes an assertion after comparison. If the signal falls inside the bounds, the assertion is true (1) and the block does nothing. If not, the block halts the simulation and returns an error message by default.

The input signal and bounds can be scalars, vectors, or matrices. All three must be the same data type. The block compares the value of the input to the bounds differently depending on the signal.

  • When comparing scalars to vectors or matrices, the block compares the scalar to each element of the non-scalar input signal or bounds.

  • When comparing vectors or matrix signals to other vectors or matrices, the block compares the input signal to the bounds element-by-element.

  • For models with more than one vector or matrix input signal or bounds, the vectors or matrices must have the same dimensions.

Ports

Input

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Input signal checked against the range specified by the Upper bound and Lower bound parameters.

Data Types: half | single | double | int8 | int16 | int32 | int64 | uint8 | uint16 | uint32 | uint64 | Boolean | fixed point | enumerated

Output

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Output signal that is true (1) if the assertion succeeds, and false (0) if the assertion fails. If, in the Configuration Parameters window, in the Math and Data Types section, under Advanced parameters, you select Implement logic signals as Boolean data, then the output data type is Boolean. Otherwise, the data type of the signal is double.

Dependencies

To enable this output port, set the Output assertion signal parameter check box.

Data Types: double | Boolean

Parameters

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Specify the upper bound on the range of amplitudes that the input signal can have.

Command-Line Information

Parameter: max
Type: character vector
Values: scalar | vector | matrix
Default: '0'

Select this check box to make the range of valid input amplitudes include the lower bound.

Command-Line Information

Parameter: min_included
Type: character vector
Values: 'on' | 'off'
Default: 'on'

Specify the lower bound on the range of amplitudes that the input signal can have.

Command-Line Information

Parameter: min
Type: character vector
Values: scalar | vector | matrix
Default: '0'

Select this check box to make the range of valid input amplitudes include the lower bound.

Command-Line Information

Parameter: min_included
Type: character vector
Values: 'on' | 'off'
Default: 'on'

Clearing this parameter disables the block and causes the model to behave as if the block does not exist. To enable or disable all verification blocks, regardless of the setting of this option, go to the Configuration Parameters window, click Diagnostics > Data Validity, expand the Advanced parameters section, and set Model Verification block enabling to Enable all or Disable all.

Command-Line Information

Parameter: enabled
Type: character vector
Values: 'on' | 'off'
Default: 'on'

Specify a MATLAB® expression to evaluate when the assertion fails. Because the expression is evaluated in the MATLAB workspace, define all variables used in the expression in that workspace.

Dependencies

To enable this parameter, select the Enable assertion parameter.

Command-Line Information

Parameter: callback
Type: character vector
Values: MATLAB expression
Default: ''

Select this parameter to stop the simulation when the check fails. Clear this parameter to display a warning and continue the simulation.

Command-Line Information

Parameter: stopWhenAssertionFail
Type: character vector
Values: 'on' | 'off'
Default: 'on'

Select this parameter to enable the output port.

Command-Line Information

Parameter: export
Type: character vector
Values: 'on' | 'off'
Default: 'off'

Specify the style of the block icon. The graphic option displays a graphical representation of the assertion condition on the icon. The text option displays a mathematical expression that represents the assertion condition.

Command-Line Information

Parameter: icon
Type: character vector
Values: 'graphic' | 'text'
Default: 'graphic'

Block Characteristics

Data Types

Boolean | double | enumerated | fixed point | half | integer | single

Direct Feedthrough

no

Multidimensional Signals

yes

Variable-Size Signals

no

Zero-Crossing Detection

no

Extended Capabilities

PLC Code Generation
Generate Structured Text code using Simulink® PLC Coder™.

Fixed-Point Conversion
Design and simulate fixed-point systems using Fixed-Point Designer™.

Introduced before R2006a