Post-Layout Verification of Parallel Link Projects
Post-layout verification allows you to verify the performance of your actual routed system against the design guidelines or specification rules. You can edit the vias and stackups and control the padstack models. You can also verify your design using PCB models. You can create topologies from extracted PCB data for pre-layout analysis.
You need a RF PCB Toolbox™ license for the post-layout workflow.
- Post-Layout Verification of Parallel Link
Verify system-level SI and timing margins of PCB design databases.
- Stackup and Extraction Control in Parallel Link Project
Edit stackups and control padstack models.
- Via and Stackup Management in Parallel Link Project
Manage vias and stackups using Stackup Editor and PadStack Editor.
- Run Incremental Simulation
Run additional nets during post-layout validation without deleting existing simulations.
- Post-Layout to Pre-Layout Extraction
Create topologies from extracted PCB data.