These options control generation of an automatic test bench that compares your generated TLM component with your Simulink® model. This test bench is not supported if you generate a TLM component for an operating system different than your MATLAB® host machine.
Use the test bench options to specify these options:
Generate testbench — Select to generate a test bench for the generated TLM component.
Generate verbose messages during testbench execution — The default is not to generate these messages.
Run-time timing mode — Specify whether the test bench executes with or without timing annotations. When you select With timing, the target annotates TLM component transactions with delays, and the initiator module honors them. The initiator module synchronizes immediately following the transaction execution.
When you select Without timing, the target does not annotate TLM component transaction with delays. The initiator module and target only perform synchronization using zero-time wait calls.
Buffer triggering modes — Specify whether the initiator controls moving datasets between the registers and the buffers or if the component moves the datasets automatically. In your TLM environment, these specifications are performed via a runtime configuration command. You can change them dynamically throughout simulation.
The default is Automatic mode. If you instead choose Manual mode, the initiator module must explicitly write a command to the command and status register to move the input data set from the register to the input buffer, or move the output data set from the output buffer to the output register.
Manual mode enables an initiator module to reuse a complete or partial input data set for a subsequent execution of the algorithm, thereby saving simulation time by avoiding data TLM component transactions don’t need. For example, if the target uses a full memory map and the initiator module detects that only one of the values is changing, the initiator module may execute TLM component transactions only for the changing value. The initiator module then writes a push command to execute the algorithm.
For this field to be enabled, select Include a command and status register in the memory map in the TLM Generation tab.
After code generation is successfully completed, you can use Verify TLM Component to perform the following actions:
Build the generated code using make and generated makefiles.
Run Simulink to capture input stimulus and expected results.
Convert the Simulink data to TLM vectors.
Run the standalone SystemC/TLM test bench executable.
Convert the TLM results back to Simulink data.
Perform a data comparison.
Generate a Figure window for any signals that had data miscompares.