setNumberofTriggerStages

Configure number of trigger stages for capturing data

Syntax

setNumberofTriggerStages(DC,N)

Description

Add-On Required: This feature requires one of these add-ons.

• HDL Verifier Support Package for Intel FPGA Boards
• HDL Verifier Support Package for AMD FPGA and SoC Devices

setNumberofTriggerStages(DC,N) specifies an integer value configures the number of trigger stages, N, for capturing data. DC is customized data capture object.

Input Arguments

DC — Customized data capture object

hdlverifier.FPGADataReader System object™

Customized data capture object, specified as an hdlverifier.FPGADataReader System object.

N — Total number of trigger stages

integer from 1 to M

Total number of trigger stages in which you want to capture the data, specified as an integer from 1 to M, where M is set by the Max trigger stages parameter of the FPGA Data Capture Component Generator tool.

Version History

Introduced in R2020b