Get Started with HDL Verifier

Tutorials

HDL Cosimulation

• Verify HDL Module with MATLAB Testbench
  This tutorial guides you through the basic steps to set up an HDL Verifier™ application that uses MATLAB® to verify a simple HDL design.
• Verify HDL Module with Simulink Testbench
  Set up an HDL Verifier session that uses Simulink to verify a simple VHDL^® model.

HDL Code Import

• Get Started with Cosimulation Wizard for MATLAB System Object
  Using HDL Verifier™, you can set up cosimulation between MATLAB® or Simulink® and an HDL simulator.
• Verify Raised Cosine Filter Design Using Simulink
  Provides instruction in using the Cosimulation Wizard to create a Simulink model for cosimulation.

FPGA-in-the-Loop (FIL)

• Verify HDL Implementation of PID Controller Using FPGA-in-the-Loop
  This example shows you how to set up an FPGA-in-the-Loop (FIL) application using HDL Verifier™.

Verify Generated HDL Code with HDL Workflow Advisor (requires HDL Coder license)

• Choose a Test Bench for Generated HDL Code (HDL Coder)
  Select a generated test bench.
• Generate Test Bench and Enable Code Coverage Using the HDL Workflow Advisor (HDL Coder)
  Generate test bench and code coverage for generated HDL code using the HDL Workflow Advisor.

About HDL Verification

• HDL Cosimulation
  

  The HDL Verifier software consists of MATLAB functions, a MATLAB System object™, and a library of Simulink blocks, all of which establish communication links between the HDL simulator and MATLAB or Simulink.

• FPGA-in-the-Loop Verification
  

  HDL Verifier works with Simulink or MATLAB and HDL Coder and the supported FPGA development environment to prepare your automatically generated HDL code for implementation in an FPGA.

• FPGA Debug
  

  HDL Verifier provides FPGA data capture and AXI manager features for debugging and testing implementations on FPGA or SoC device from MATLAB or Simulink.

• TLM Component Generation
  

  HDL Verifier lets you create a SystemC Transaction Level Model (TLM) that can be executed in any OSCI-compatible TLM 2.0 environment, including a commercial virtual platform.

• SystemVerilog DPI Component Generation
  

  HDL Verifier works with Simulink Coder™ or MATLAB Coder to export a subsystem as generated C code inside a SystemVerilog component with a Direct Programming Interface (DPI).

Featured Examples

Get Started with Cosimulation Wizard for MATLAB System Object

Using HDL Verifier™, you can set up cosimulation between MATLAB® or Simulink® and an HDL simulator. The Cosimulation Wizard is a graphical user interface (GUI) that takes HDL code as input and generates a cosimulation block or System object™ as output. The System object allows cosimulating HDL within MATLAB, and the block allows cosimulating HDL within Simulink.

• Open Live Script

Get Started with Simulink HDL Cosimulation

Set up an HDL Verifier™ application using the Cosimulation Wizard in the Simulink® environment.

• Open Live Script

Comparing HDL and Simulink Code Coverage Using Cosimulation

Achieve complete code coverage of an HDL cruise controller design using Simulink® and an HDL Simulator.

• Open Script

Get Started with SystemVerilog DPI Component Generation

Generate a SystemVerilog DPI component from a proportional-integral-derivative (PID) controller in a Simulink® model and how to export the component to an HDL simulator.

• Open Model

Get Started with MATLAB Based SystemVerilog DPI Generation

Generate a SystemVerilog DPI component for a programmable square-wave generator written in MATLAB®, and export it to an HDL simulator.

• Open Script

Capture Temperature Sensor Data from AMD FPGA Board Using FPGA Data Capture

Use FPGA data capture with existing HDL design to capture FPGA internal signals over a JTAG or Ethernet connection.

• Open Script

Access FPGA Memory Using JTAG-Based AXI Manager

Use JTAG-based AXI manager to access memories connected to an FPGA.

• Open Script

Videos

HDL Verifier Overview
Test and verify Verilog^® and VHDL designs for FPGAs, ASICs, and SoCs with HDL Verifier. Verify RTL with testbenches running in MATLAB or Simulink using cosimulation with HDL simulators. Use these same testbenches with FPGA and SoC development boards to verify HDL implementations in hardware.