The coder supports HDL code generation for direct form FIR polyphase sample rate
converters. dsp.FIRRateConverter
is a multirate filter
structure that combines an interpolation factor and a decimation factor. This combination
enables you to perform fractional interpolation or decimation on an input signal.
The interpolation factor (l
) and decimation factor
(m
) for a polyphase sample rate converter are specified as integers in
the InterpolationFactor
and DecimationFactor
properties of a dsp.FIRRateConverter
System object™. This code constructs an object with a resampling ratio of
5/3:
frac_cvrter = dsp.FIRRateConverter('InterpolationFactor',5, ... 'DecimationFactor',3)
Fractional rate resampling can be visualized as a two-step process: interpolation by the
factor l
, followed by decimation by the factor m
. For
a resampling ratio of 5/3, the object raises the sample rate by a factor of 5 using a
five-path polyphase filter. A resampling switch then reduces the new rate by a factor of 3.
This process extracts five output samples for every three input samples.
For general information on this filter structure, see the dsp.FIRRateConverter
reference page in the DSP System Toolbox™ documentation.
The signal flow for the dsp.FIRRateConverter
filter
is similar to the polyphase FIR interpolator (dsp.FIRInterpolator
). The delay line is advanced to deliver each input after
the required set of polyphase coefficients are processed.
The diagram illustrates the timing of the HDL implementation for dsp.FIRRateConverter
. A clock enable input
(ce_in
) indicates valid input samples. The output data, and a clock
enable output (ce_out
), are produced and delivered simultaneously,
which results in a nonperiodic output.
The clock rate required to process the hardware logic is related to the input rate as:
ceil(InterpolationFactor/DecimationFactor)
For a resampling ratio of 5/3, the clock rate is ceil(5/3) = 2
, or
twice the input sample rate. The inputs are delivered at every other clock cycle. The
outputs are delivered as they are produced and therefore are nonperiodic.
Note
When the generated code or hardware logic is deployed, the outputs must be taken into a FIFO designed with outputs occurring at the desired sampling rate.
The HDL entity or module generated from the dsp.FIRRateConverter
filter has one input and two output clock enable
ports:
Clock enable outputs: The default clock enable output port name is
ce_out
. This signal indicates when the output data sample is
valid. As with other multirate filters, you can use the Clock enable output
port field on the Global Settings >
Ports tab of the Generate HDL dialog box to specify the port
name. Alternatively, you can use the ClockEnableOutputPort
property to set the port name in the
generatehdl
command.
The filter also passes through the clock enable input to an output port named
ce_in
. This signal indicates when the object accepted an input
sample. You can use this signal to control the upstream data flow. You cannot
customize this port name.
Clock enable input: The default clock enable input port name is
clk_enable
. This signal indicates when the input data sample is
valid. You can use the Clock enable input port field on the
Global Settings tab of the Generate HDL dialog box to specify
the port name. Alternatively, you can use the ClockEnableInputPort
property to set the port name in the
generatehdl
command.
Generated test benches apply the test vectors at the correct rate, then observe and verify the output as it is available. The test benches control the data flow using the input and output clock enables.
The following example constructs a fixed-point dsp.FIRRateConverter
object with a resampling ratio of 5/3, and generates
VHDL filter code. When you generate HDL code for a System object, specify the input fixed-point data type. The object determines internal
data types based on the input type and property
settings.
frac_cvrter = dsp.FIRRateConverter('InterpolationFactor',5,'DecimationFactor',3) generatehdl(frac_cvrter,'InputDataType',numerictype(1,16,15))
### Starting VHDL code generation process for filter: filter ### Generating: H:\hdlsrc\filter.vhd ### Starting generation of filter VHDL entity ### Starting generation of filter VHDL architecture ### Successful completion of VHDL code generation process for filter: filter ### HDL latency is 2 samples
The following code generation options are not supported for dsp.FIRRateConverter
filters:
Use of pipeline registers (AddPipelineRegisters
)
Distributed Arithmetic architecture (DARadix
and (DALUTPartition
))
Fully or partially serial architectures (SerialPartition
and
ReuseAccum
)
Multiple clock inputs (ClockInputs
)