Set up a writable working folder outside your MATLAB® installation
folder to store files that will be generated as you complete your
tutorial work. The tutorial instructions assume that you create the
hdlfilter_tutorials on drive C.
This section assumes that you are familiar with the MATLAB user interface and the Filter Designer. The following instructions guide you through the procedure of designing and creating a basic FIR filter using Filter Designer:
Start the MATLAB software.
Set your current folder to the folder you created in Create a Folder for Your Tutorial Files.
Start Filter Designer by entering the
filterDesigner command in the
MATLAB Command Window. The Filter Design & Analysis Tool
dialog box appears.
In the Filter Design & Analysis Tool dialog box, check that the following filter options are set:
|Filter Order||Minimum order|
|Options||Density Factor: |
These settings are for the default filter design that the Filter Designer creates for you. If you do not have to change the filter, and Design Filter is grayed out, you are done and can skip to Quantize the Filter.
If you modified options listed in step 4, click Design Filter. The Filter Designer creates a filter for the specified design and displays the following message in the Filter Designer status bar when the task is complete.
Designing Filter... Done
For more information on designing filters with the Filter Designer, see the DSP System Toolbox™ documentation.
You must quantize filters for HDL code generation. To quantize your filter,
Open the basic FIR filter design you created in Design a FIR Filter in Filter Designer.
Click the Set Quantization Parameters button in the left-side toolbar. The Filter Designer displays a Filter arithmetic menu in the bottom half of its dialog box.
the Filter arithmetic list. Then select
all from the Filter
precision list. The Filter Designer displays the first
of three tabbed panels of quantization parameters across the bottom
half of its dialog box.
Use the quantization options to test the effects of various settings on the performance and accuracy of the quantized filter.
Set the quantization parameters as follows:
|Coefficients||Numerator word length|
|Best-precision fraction lengths|
|Use unsigned representation|
|Scale the numerator coefficients to fully utilize the entire dynamic range|
|Input/Output||Input word length|
|Input fraction length|
|Output word length|
|Filter Internals||Rounding mode|
|Accum. word length|
For more information on quantizing filters with the Filter Designer, see the DSP System Toolbox documentation.
After you quantize your filter, you are ready to configure coder options and generate VHDL code for the filter. This section guides you through starting the Filter Design HDL Coder™ UI, setting options, and generating the VHDL code and test bench for the basic FIR filter you designed and quantized in Design a FIR Filter in Filter Designer and Quantize the Filter.
Start the Filter Design HDL Coder UI by selecting Targets > Generate HDL in the Filter Designer dialog box. The Filter Designer displays the Generate HDL dialog box.
Find the Filter Design HDL Coder online help.
In the MATLAB window, click the Help button in the toolbar or click Help > Product Help.
In the Contents pane of the Help browser, select the Filter Design HDL Coder entry.
Minimize the Help browser.
In the Generate HDL dialog box, click the Help button. A small context-sensitive help window opens. The window displays information about the dialog box.
Close the Help window.
Place your cursor over the Folder label or text box in the Target pane of the Generate HDL dialog box, and right-click. A What's This? button appears.
Click What's This? The context-sensitive help window displays information describing the Folder option. Configure the contents and style of the generated HDL code, using the context-sensitive help to get more information as you work. A help topic is available for each option.
In the Name text box of the Target pane,
replace the default name with
basicfir. This option
names the VHDL entity and the file that contains the VHDL code for
Select the Global settings tab of the UI. Then select the
General tab of the Additional
settings section of the UI. Type
Tutorial - Basic
FIR Filter in the Comment in header text
box. The coder adds the comment to the end of the header comment block in
each generated file.
Select the Ports tab of the Additional settings section of the UI.
Change the names of the input and output ports. In
the Input port text box, replace
In the Output port text box, replace
Clear the check box for the Add input register option. The Ports pane now looks like the following.
Click the Test Bench tab in the
Generate HDL dialog box. In the File name text
box, replace the default name with
This option names the generated test bench file.
Click Generate to start the code generation process.
The coder displays messages in the MATLAB Command Window as it generates the filter and test bench VHDL files:
### Starting VHDL code generation process for filter: basicfir ### Generating: C:\hdlfilter_tutorials\hdlsrc\basicfir.vhd ### Starting generation of basicfir VHDL entity ### Starting generation of basicfir VHDL architecture ### HDL latency is 2 samples ### Successful completion of VHDL code generation process for filter: basicfir ### Starting generation of VHDL Test Bench ### Generating input stimulus ### Done generating input stimulus; length 3429 samples. ### Generating Test bench: C:\hdlfilter_tutorials\hdlsrc\basicfir_tb.vhd ### Please wait ... ### Done generating VHDL Test Bench
As the messages indicate, the coder creates the folder
your current working folder and places the files
Observe that the messages include hyperlinks to the generated code and test bench files. By clicking these hyperlinks, you can open the code files directly into the MATLAB Editor.
The generated VHDL code has the following characteristics:
VHDL entity named
Registers that use asynchronous resets when the reset signal is active high (1).
Ports have the following names:
|Clock enable input|
An extra register for handling filter output.
Clock input, clock enable input, and reset ports are
STD_LOGIC and data input and output ports
are of type
Coefficients are named
n is the coefficient number, starting
is used when zeros are concatenated:
'0' & '0'...
Registers are generated with the statement
clk'event AND clk='1' THEN rather than with the
'_process' is appended
to process names.
The generated test bench:
Is a portable VHDL file.
Forces clock, clock enable, and reset input signals.
Forces the clock enable input signal to active high.
Drives the clock input signal high (1) for 5 nanoseconds and low (0) for 5 nanoseconds.
Forces the reset signal for two cycles plus a hold time of 2 nanoseconds.
Applies a hold time of 2 nanoseconds to data input signals.
For a FIR filter, applies impulse, step, ramp, chirp, and white noise stimulus types.
When you have finished generating code, click Close to close the Generate HDL dialog box.
Get familiar with the generated VHDL code by opening and browsing
through the file
basicfir.vhd in an ASCII or HDL
Open the generated VHDL filter file
basicfir. This line identifies the VHDL module, using the value
you specified for the Name option in the
Target pane. See step 5 in Configure and Generate VHDL Code.
Tutorial. This section is where the coder places the text you
entered for the Comment in header option. See step 10
in Configure and Generate VHDL Code.
HDL Code. This section lists coder options you modified in Configure and Generate VHDL Code.
ENTITY. This line names the VHDL entity, using the value you
specified for the Name option in the
Target pane. See step 5 in Configure and Generate VHDL Code.
PORT declaration defines the
clock, clock enable, reset, and data input and output ports. The ports for
clock, clock enable, and reset signals are named with default character
vectors. The ports for data input and output are named as you specified on
the Input port and Output port
options on the Ports tab of the Generate HDL dialog
box. See step 12 in Configure and Generate VHDL Code.
Constants. This section
defines the coefficients. They are named using the default naming
the coefficient number, starting with 1.
Signals. This section
of code defines the signals for the filter.
Delay_Pipeline_process includes the default
IF reset. This code
asserts the reset signal. The default, active high (1), was specified.
Also note that the
PROCESS block applies the default
asynchronous reset style when generating VHDL code for registers.
ELSIF. This code checks
for rising edges when the filter operates on registers. The default
clk'event statement is used instead of the optional
Output_Register. This section of code writes the filter data to
an output register. Code for this register is generated by default. In step
13 in Configure and Generate VHDL Code,
you cleared the Add input register option, but left the
Add output register selected. Also note that the
PROCESS block name
Output_Register_process includes the default
PROCESS block postfix
data_out. This section
of code drives the output data of the filter.
This section explains how to verify the generated VHDL code for the basic FIR filter with the generated VHDL test bench. This tutorial uses the Mentor Graphics® ModelSim® software as the tool for compiling and simulating the VHDL code. You can also use other VHDL simulation tool packages.
To verify the filter code, complete the following steps:
Start your Mentor Graphics ModelSim simulator.
Set the current folder to the folder that contains your generated VHDL files. For example:
If desired, create a design library to store the compiled VHDL entities, packages,
architectures, and configurations. In the
ModelSim simulator, you can create a design library with the
Compile the generated filter and test bench VHDL files. In the
ModelSim simulator, you compile VHDL code with the
vcom command. The following commands compile the
filter and filter test bench VHDL code.
vcom basicfir.vhd vcom basicfir_tb.vhd
The following screen display shows this command sequence and informational messages displayed during compilation.
Load the test bench for simulation. The procedure for loading the test bench varies depending
on the simulator you are using. In the
ModelSim simulator, you load the test bench for simulation with the
vsim command. For example:
The following figure shows the results of loading
work.basicfir_tb with the
Open a display window for monitoring the simulation as the test bench runs. In the Mentor Graphics ModelSim simulator, use the following command to open a wave window and view the results of the simulation as HDL waveforms.
The following wave window displays.
To start running the simulation, issue the start simulation command for your simulator. For
example, in the
ModelSim simulator, you can start a simulation with the
The following display shows the
command being used to start a simulation.
As your test bench simulation runs, watch for error messages. If error messages appear, interpret them as they pertain to your filter design and the HDL code generation options you selected. Determine whether the results are expected based on the customizations you specified when generating the filter VHDL code.
The following wave window shows the simulation results as HDL waveforms.