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RAM Mapping Parameters

This page describes configuration parameters that reside in the HDL Code Generation > Optimization > General tab of the Configuration Parameters dialog box. Using the parameters in this section, you can reduce the area usage on the target device by trading-off block RAMs for registers. The parameters specify whether you want to map pipeline registers in the generated code to RAM, and the minimum RAM size for mapping to block RAMs on the FPGA.

Map pipeline delays to RAM

Map pipeline registers in the generated HDL code to RAM. Certain speed or area optimizations such as pipelining and resource sharing, or certain block implementations that you specify can insert pipeline registers in the generated HDL code. You can save area on the target device by mapping these pipeline registers to RAM.

Settings

Default: Off

On

Map pipeline registers in the generated HDL code to RAM. To map these registers to block RAMs, the RAM size must be greater than or equal to the RAM mapping threshold in bits. To calculate the total RAM size for delays, use this formula: 

RAMSize = Delay length * Word length * Vector length * Complexity
Complexity is 2 for a complex data type or 1 for a real datatype.

Off

Do not map pipeline registers in the generated HDL code to RAM.

Command-Line Information

Property: MapPipelineDelaysToRAM
Type: character vector
Value: 'on' | 'off'
Default: 'off'

To set this property, use the functions hdlset_param or makehdl. To view the property value, use the function hdlget_param.

For example, you can enable the MapPipelineDelaysToRAM setting when you generate HDL code for the symmetric_fir subsystem inside the sfir_fixed model using either of these methods.

  • Pass the property as an argument to the makehdl function.

    makehdl('sfir_fixed/symmetric_fir', ... 
        'MapPipelineDelaysToRAM','on')

  • When you use hdlset_param, you can set the parameter on the model and then generate HDL code using makehdl.

    hdlset_param('sfir_fixed','MapPipelineDelaysToRAM','on')
makehdl('sfir_fixed/symmetric_fir')

See Also

RAM mapping threshold

Specify the minimum RAM size for mapping to block RAMs. HDL Coder™ determines whether to use registers or RAM resources on the FPGA by comparing the RAM size of your design with the RAM mapping threshold that you specify.

You can specify the RAM mapping threshold by using either:

  • A single integer to map any delay or persistent array greater than the threshold bit size to RAM.

  • A string of format MxN that specifies two thresholds where M is the delay length (for delays) or array size (for persistent array variables) and N is the word length or bit width of the data type. Setting both thresholds excludes delays or persistent arrays that inefficiently map to block RAM on your target hardware. For more information, see Use the RAM Mapping Threshold.

Settings

Default: 256

The RAM mapping threshold must be:

  • An integer greater than or equal to zero.

  • A string that has the format MxN, where M is the delay length or array size and N is the word length.

HDL Coder uses the threshold to determine whether or not to map the following elements to block RAMs instead of to registers:

Command-Line Information

Property: RAMMappingThreshold
Type: integer, string
Value: integer greater than or equal to 0, string of MxN format
Default: 256

To set this property, use the functions hdlset_param or makehdl. To view the property value, use the function hdlget_param.

For example, you can set the RAMMappingThreshold to 1024 when you generate HDL code for the symmetric_fir subsystem inside the sfir_fixed model using either of these methods.

  • Pass the property as an argument to the makehdl function.

    makehdl('sfir_fixed/symmetric_fir', ... 
        RAMMappingThreshold=1024)

  • When you use hdlset_param, you can set the parameter on the model and then generate HDL code using makehdl.

    hdlset_param('sfir_fixed',RAMMappingThreshold=1024)
makehdl('sfir_fixed/symmetric_fir')

For example, you can set the RAMMappingThreshold to a delay length of 500 cycles and a word length of 50 bits, "500x50", when you generate HDL code for the symmetric_fir subsystem inside the sfir_fixed model using either of these methods.

  • Pass the property as an argument to the makehdl function.

    makehdl('sfir_fixed/symmetric_fir', ... 
        RAMMappingThreshold="500x50")

  • When you use hdlset_param, you can set the parameter on the model and then generate HDL code using makehdl.

    hdlset_param('sfir_fixed', RAMMappingThreshold="500x50");
makehdl('sfir_fixed/symmetric_fir')

See Also