SystemVerilog file extension

File name extension for generated SystemVerilog files

Since R2023b

Model Configuration Pane: Global Settings / General

Description

Specify the file name extension for generated SystemVerilog files.

Dependencies

To enable this option, set the target language to SystemVerilog. You can specify the target language by using the Language parameter in the HDL Code Generation pane.

Settings

.sv (default) | character vector

Default: .sv

This field specifies the file name extension for generated SystemVerilog files.

Tips

To set this property, use the functions hdlset_param or makehdl. To view the property value, use the function hdlget_param.

For example, you can specify this property when you generate HDL code for the symmetric_fir subsystem inside the sfir_fixed model using either of these methods.

• Pass the property as an argument to the makehdl function.

  makehdl('sfir_fixed/symmetric_fir', ... 
          'SystemVerilogFileExtension','.sv')

• When you use hdlset_param, you can set the parameter on the model and then generate HDL code using makehdl.

  hdlset_param('sfir_fixed','SystemVerilogFileExtension','.sv')
  makehdl('sfir_fixed/symmetric_fir')

Recommended Settings

No recommended settings.

Programmatic Use

Parameter: SystemVerilogFileExtension

Type: character vector

Default: '.sv'

Version History

Introduced in R2023b