Map lookup tables to RAM

Lookup tables in your design to block RAM and reduce area usage on the target FPGA device

Since R2021b

Model Configuration Pane: Optimization / Pipielining

Description

Use this parameter to map lookup tables in your design to block RAM and reduce area usage on the target FPGA device.

Dependencies

When you specify this parameter, in the HDL Code Generation > Target pane, specify the Synthesis Tool.

Settings

On (default) | Off

On

Map lookup tables in your design to RAM.

Off

Do not map lookup tables in your design to RAM.

Tips

To set this property, use the functions hdlset_param or makehdl. To view the property value, use the function hdlget_param.

For example, see Generate FPGA Block RAM from Lookup Tables.

Recommended Settings

No recommendations.

Programmatic Use

Parameter: LUTMapToRAM

Type: character vector

Value: 'on' | 'off'

Default: 'on'

Version History

Introduced in R2021b