Enumerated Type Encoding Scheme

Specify encoding scheme to use for enumeration types

Model Configuration Pane: Global Settings / Coding style

Description

Specify the encoding scheme to represent enumeration types in the generated HDL code. The generated HDL code for enumeration types varies based on the selected encoding scheme and the target language.

HDL Coder™ generates custom enumeration types in sorted order in the HDL code, not in the order in which you declare them.

Note

Avoid using custom enumerated values directly in mathematical computations. Depending on the encoding scheme, the numeric values assigned to enumeration members may change in the generated code.

Settings

default (default) | onehot | twohot | binary

Default: default

Use a default, onehot, twohot, or binary encoding scheme to represent enumerated types in the generated HDL code.

default

HDL Coder uses decimal encoding for Verilog^®, SystemVerilog and VHDL-native enumerated types in VHDL^®.

When you set the Language configuration parameter to Verilog or SystemVerilog, the HDL Coder emits custom enumeration values in the generated code.

When you set the Language configuration parameter to VHDL, HDL Coder uses custom enumeration values only to sort the members.

This example shows a Verilog code snippet of this encoding scheme for a Stateflow^® Chart that has four states.

parameter 
is_Chart_IN_s_idle = 2'd0, 
is_Chart_IN_s_rx = 2'd1, 
is_Chart_IN_s_wait_0 = 2'd2, 
is_Chart_IN_s_wait_tb = 2'd3;

onehot

HDL Coder uses a one-hot encoding scheme where a single bit is high to represent each enumeration value. This example shows the Verilog code snippet of this encoding scheme for a Stateflow Chart that has four states.

parameter 
is_Chart_IN_s_idle = 4'b0001, 
is_Chart_IN_s_rx = 4'b0010, 
is_Chart_IN_s_wait_0 = 4'b0100, 
is_Chart_IN_s_wait_tb = 4'b1000;

This encoding scheme does not support more than 64 enumeration values or numbers of states.

twohot

HDL Coder uses a two-hot encoding scheme where two bits are high to represent each enumeration value. This example shows the Verilog code snippet of this encoding scheme for a Stateflow Chart that has four states.

parameter 
is_Chart_IN_s_idle = 4'b0011, 
is_Chart_IN_s_rx = 4'b0101, 
is_Chart_IN_s_wait_0 = 4'b0110, 
is_Chart_IN_s_wait_tb = 4'b1001;

binary

HDL Coder uses a binary encoding scheme to represent each enumeration value. This example shows the Verilog code snippet of this encoding scheme for a Stateflow Chart that has four states.

parameter 
is_Chart_IN_s_idle = 2'b00, 
is_Chart_IN_s_rx = 2'b01, 
is_Chart_IN_s_wait_0 = 2'b10, 
is_Chart_IN_s_wait_tb = 2'b11;

In VHDL, HDL Coder uses CONSTANT types to encode nondefault enumeration values in the generated code. For example, this code snippet shows the generated VHDL code when you use the two-hot state encoding for a Stateflow Chart that has four states.

 PACKAGE s_pkg IS
  -- Constants
  -- Two-hot encoded enumeration values for type state_type_is_Chart
  CONSTANT IN_s_idle         : std_logic_vector(3 DOWNTO 0) := 
    "0011";
  CONSTANT IN_s_rx           : std_logic_vector(3 DOWNTO 0) := 
    "0101";
  CONSTANT IN_s_wait_0       : std_logic_vector(3 DOWNTO 0) := 
    "0110";
  CONSTANT IN_s_wait_tb      : std_logic_vector(3 DOWNTO 0) := 
    "1001";

END s_pkg;

Tips

To set this property, use the functions hdlset_param or makehdl. To view the property value, use the function hdlget_param.

Recommended Settings

No recommended settings.

Programmatic Use

Parameter: EnumEncodingScheme

Type: character vector

Value: 'default' | 'onehot' | 'twohot' | 'binary'

Default: 'default'

Version History

Introduced in R2017b