Clock inputs

Generate single or multiple clock inputs

Model Configuration Pane: HDL Code Generation / Global Settings

Description

The Clock inputs parameter specifies whether to generate single or multiple clock inputs for the design under test (DUT).

Settings

Single (default) | Multiple

Single

Generate a single clock input for the DUT. If the DUT is multirate, the input clock is the primary clock rate, and HDL Coder™ synthesizes a timing controller to generate additional clocks as required. This is the recommended setting for your design.

Multiple

Generate a unique clock for each Simulink^® rate in the DUT. The number of timing controllers generated depends on the contents of the DUT. The Oversampling factor must be 1 to specify multiple clocks.

To generate clock for each Simulink rate in a multirate model, include sequential logic block, such as a Delay block, at each Simulink rate. If you do not include sequential logic for a Simulink rate, HDL Coder does not generate the clock signal for that rate.

Tips

To set this property, use the functions hdlset_param or makehdl. To view the property value, use the function hdlget_param.

For example, to set this property for a subsystem named symmetric_fir in a model named sfir_fixed, use one of these methods:

• Pass the property as an argument to the makehdl function.

  makehdl("sfir_fixed/symmetric_fir","ClockInputs","Multiple")

• Use hdlset_param to set the parameter on the model and then generate HDL code using makehdl.

  hdlset_param("sfir_fixed","ClockInputs","Multiple")
  makehdl("sfir_fixed/symmetric_fir")

Programmatic Use

Parameter: ClockInputs

Type: character vector

Value: "Single" | "Multiple"

Default: "Single"

Version History

Introduced in R2012a