Embedded Target Features for Altera SoC Platform

R2026b

With HDL Coder™ Support Package for Intel^® FPGA and SoC Devices, you can use the supported hardware with these MathWorks^® software capabilities:

• Automated makefile-based software system that builds, downloads to, and runs on hardware (Build and Run Executable on Altera SoC Platform).

• Multitasking code generation that uses POSIX threads (Pthreads) for concurrent execution on ARM^® cores running Linux^® (Multicore Processor Targets).

• Tuning and monitoring the executable running on the hardware from a Simulink^® model (Host-Target Communication with External Mode Simulation).

• Model referencing using the Model block (Referenced Models (Embedded Coder)).

• Processor-in-the-loop (PIL) simulation using model blocks and a TCP/IP connection (Create a Target Communication Channel for Processor-in-the-Loop (PIL) Simulation (Embedded Coder)).

• PIL-based execution profiling (Code Verification Through Software-in-the-Loop and Processor-in-the-Loop Execution (Embedded Coder)).

• Code-replacement library for ARM Cortex-A9 processor (Optimize Code for ARM Cortex-A Processors (Embedded Coder)).

Also, the Block Library for Altera^® SoC platform provides:

• Exchange data with the programmable logic IP core using the AXI4 Read and AXI4 Write blocks.

• Network communications using the UDP Send and UDP Receive blocks.

• Linux task management using the Linux Task block.

Note

PIL simulation and PIL-based execution profiling require single-core execution.