Channel 16-31

R2026b

Set ADC sample state count for channels 16 through 31

Since R2026b

Model Configuration Pane: Hardware Implementation / Embedded Coder Hardware Support Package / Hardware board settings / Target hardware resources / ADC

Description

Specify the number of sampling clock cycles for the ADC sample-and-hold phase for channels 16 through 31 as a group. A higher value increases the sampling time, which can improve conversion accuracy for high-impedance analog sources.

Unlike channels 0 through 15, which are configured individually, channels 16 through 31 share a single sample state count value.

Dependencies

To enable this parameter, select the Set sample state counts of channels parameter.

Settings

7 (default)

Specify a positive integer value representing the number of sampling clock cycles.

Recommended Settings

No recommendation.

Programmatic Use

No programmatic use is available.

Version History

Introduced in R2026b

See Also