FIR Interpolator
Libraries:
DSP HDL Toolbox /
Filtering
Description
The FIR Interpolator block implements a singlerate polyphase FIR interpolation filter that is optimized for HDL code generation. The block provides a hardwarefriendly interface with input and output control signals. To provide a cycleaccurate simulation of the generated HDL code, the block models architectural latency including pipeline registers and resource sharing.
The block accepts scalar or vector input and outputs a scalar or vector depending on the interpolation factor and the number of cycles between input samples. The block implements a polyphase decomposition with InterpolationFactor subfilters. The filter can implement a serial architecture if there is regular spacing between input samples.
The block provides two filter structures. The direct form systolic architecture provides an implementation that makes efficient use of Intel^{®} and Xilinx^{®} DSP blocks. This architecture can be fullyparallel or serial. To use a serial architecture, the input samples must be spaced out with a regular number of invalid cycles between the valid samples. The direct form transposed architecture is a fully parallel implementation that is suitable for FPGA and ASIC applications. For a filter implementation that matches multipliers, pipeline registers, and preadders to the DSP configuration of your FPGA vendor, specify your target device when you generate HDL code.
All filter structures optimize hardware resources by sharing multipliers for symmetric or antisymmetric filters and by removing the multipliers for zerovalued coefficients such as in halfband filters and Hilbert transforms.
Examples
Ports
Input
data — Input data
real or complex scalar or vector
Input data, specified as a real or complex scalar or vector. The vector size must be less than or equal to 64.
When the input data type is an integer type or a fixedpoint type, the block uses fixedpoint arithmetic for internal calculations and provides parameters on the Data Types tab to customize the data types. When the input data type is a floatingpoint type, the block uses that input floatingpoint type for internal calculations and the output data type.
The software supports double
and
single
data types for simulation, but not for HDL code generation.
Data Types: fixed point
 single
 double
 int8
 int16
 int32
 uint8
 uint16
 uint32
Complex Number Support: Yes
valid — Indicates valid input data
scalar
Control signal that indicates if the input data is valid. When
valid is 1
(true
), the
block captures the values from the input data port. When
valid is 0
(false
), the
block ignores the values from the input data port.
Data Types: Boolean
reset — Clears internal states
scalar
Control signal that clears internal states. When reset is
1
(true
), the block stops the current
calculation and clears internal states. When the reset is
0
(false
) and the input
valid is 1
(true
), the
block captures data for processing.
For more reset considerations, see the Reset Signal section on the Hardware Control Signals page.
Dependencies
To enable this port, on the Control Ports tab, select Enable reset input port.
Data Types: Boolean
Output
data — Interpolated output data
real or complex scalar or vector
Interpolated output data, returned as a real or complex scalar or vector. The
vector size is InputSize * InterpolationFactor.
When NumCycles is greater than
InterpolationFactor, scalar output samples are spaced with
floor(NumCycles/InterpolationFactor)
invalid cycles, and the output valid signal indicates which
samples are valid after interpolation.
When the input data type is a floatingpoint type, the output data inherits the data type of the input data. When the input data type is an integer type or a fixedpoint type, the Output parameter on the Data Types tab controls the output data type.
Data Types: fixed point
 single
 double
 int8
 int16
 int32
 uint8
 uint16
 uint32
Complex Number Support: Yes
valid — Indicates valid output data
scalar
Control signal that indicates if the data from the output
data port is valid. When valid is
1
(true
), the block returns valid data from
the output data port. When valid is
0
(false
), the values from the output
data port are not valid.
Data Types: Boolean
ready — Indicates block is ready for new input data
scalar
Control signal that indicates that the block is ready for new input data sample on
the next cycle. When ready is 1
(true
), you can specify the data
and valid inputs for the next time step. When
ready is 0
(false
), the block ignores any input data in the next time step.
Data Types: Boolean
Parameters
Main
Coefficients — FIR filter coefficients
fir1(35,0.4)
(default)  real or complexvalued vector
FIR filter coefficients, specified as a real or complexvalued vector. You can specify the vector as a workspace variable or as a call to a filter design function. When the input data type is a floatingpoint type, the block casts the coefficients to the same data type as the input. When the input data type is an integer type or a fixedpoint type, set the data type for the coefficients on the Data Types tab.
Example: firpm(30,[0 0.1 0.2 0.5]*2,[1 1 0 0])
defines
coefficients by using a linearphase filter design function.
Complex Number Support: Yes
Filter structure — HDL filter architecture
Direct form systolic
(default)  Direct form transposed
Specify the HDL filter architecture as one of these structures:
Direct form systolic
— This architecture provides a parallel or partly serial filter implementation that makes efficient use of Intel and Xilinx DSP HDL blocks. For a partly serial implementation, specify a value greater than 1 for the Minimum number of cycles between valid input samples parameter. You cannot use framebased input with the partly serial architecture.Direct form transposed
— This architecture is a fully parallel implementation that is suitable for FPGA and ASIC applications.
The block implements a polyphase decomposition filter by using Discrete FIR Filter blocks. Each filter phase shares resources internally where coefficients and serial options allow. For architecture details, see FIR Filter Architectures for FPGAs and ASICs. When you use a partlyserial systolic architecture and Minimum number of cycles between valid input samples is larger than the filter length divided by the interpolation factor, the block interleaves each phase of coefficients over a single FIR filter to share resources between phases.
Interpolation factor — Interpolation factor
2 (default)  integer greater than two
Specify an integer interpolation factor greater than two. The output vector size is InputSize * InterpolationFactor. The output vector size must be less than 64 samples.
Minimum number of cycles between valid input samples — Serialization requirement for input timing
1
(default)  positive integer
Serialization requirement for input timing, specified as a positive integer. This parameter represents N, the minimum number of cycles between valid input samples. When you set Minimum number of cycles between valid input samples greater than the filter length, L, and the input and coefficients are both real, the filter uses a single multiplier.
Because the block applies coefficient optimizations before serialization, the sharing factor of the final filter can be lower than the number of cycles that you specified.
Dependencies
To enable this parameter, set Filter structure to
Direct form systolic
.
You cannot use framebased input with Minimum number of cycles between valid input samples greater than 1.
Data Types
Rounding mode — Rounding mode for typecasting the output
Floor
(default)  Ceiling
 Convergent
 Nearest
 Round
 Zero
Rounding mode for typecasting the output to the data type specified by the Output parameter. When the input data type is floating point, the block ignores this parameter. For more details, see Rounding Modes.
Saturate on integer overflow — Overflow handling for typecasting the output
off
(default)  on
Overflow handling for typecasting the output to the data type specified by the Output parameter. When the input data type is floating point, the block ignores this parameter. For more details, see Overflow Handling.
Coefficients — Data type of filter coefficients
Inherit: Same word length as
input
(default)  <data type expression>
When the input is a fixedpoint or integer type, the block casts the filter coefficients using the rule or data type in this parameter.. The quantization rounds to the nearest representable value and saturates on overflow. When the input data type is a floatingpoint type, the block ignores this parameter and all internal arithmetic uses the same data type as the input.
The recommended data type for this parameter is Inherit: Same word
length as input
.
The block returns a warning or error if either of these conditions occur.
The coefficients data type does not have enough fractional length to represent the coefficients accurately.
The coefficients data type is unsigned, and the coefficients include negative values.
Output — Data type of filter output
Inherit: Inherit via internal
rule
(default)  Inherit: Same word length as input
 <data type expression>
When the input is a fixedpoint or integer type, the block casts the output of the filter using the rule or data type in this parameter. The quantization uses the settings of the Rounding mode and Overflow mode parameters. When the input data type is floating point, the block ignores this parameter and returns output in the same data type as the input.
The block increases the word length for full precision inside each filter tap and casts the final output to the specified type. The maximum final internal data type (WF) depends on the input data type (WI), the coefficient data type (WC), and the number of coefficients (L) and is given by
WF = WI + WC +
ceil(log2(L))
.
Because the coefficient values limit the potential growth, usually the actual fullprecision internal word length is smaller than WF.
Control Ports
Enable reset input port — Option to enable reset input port
off
(default)  on
Select this check box to enable the reset input port. The reset signal implements a local synchronous reset of the data path registers.
For more reset considerations, see the Reset Signal section on the Hardware Control Signals page.
Use HDL global reset — Option to connect data path registers to generated HDL global reset signal
off
(default)  on
Select this check box to connect the generated HDL global reset signal to the data path registers. This parameter does not change the appearance of the block or modify simulation behavior in Simulink^{®}. When you clear this check box, the generated HDL global reset clears only the control path registers. The generated HDL global reset can be synchronous or asynchronous depending on the HDL Code Generation > Global Settings > Reset type parameter in the model Configuration Parameters.
For more reset considerations, see the Reset Signal section on the Hardware Control Signals page.
Algorithms
The block implements a polyphase filter bank where the filter coefficients are decomposed into InterpolationFactor subfilters. If the filter length is not divisible by the Interpolation factor parameter value, then the block zeropads the coefficients. When your input is regularly spaced, with two or more cycles between valid samples, as indicated by the Minimum number of cycles between valid input samples parameter, the filter can share multiplier resources in time.
This flow chart shows which filter architectures result from your parameter settings. It also shows the number of multipliers used by the filter implementation. The filter architecture depends on the input frame size, V, the interpolation factor, R, the number of cycles between valid input samples, N, and the number of filter coefficients, L. The architectures are in order from lowest resource use on the left, to higher resources on the right. The higher resource architectures are trading off resource use for higher throughput. Each architecture is described below the flow chart.
The number of multipliers shown in the flow chart is for filters with real input and real coefficients. For complex input, the filter uses three times as many multipliers.
Architectures 1 and 2 — Serial polyphase interleaved filter bank.
When NumCycles is greater than FilterLength/InterpolationFactor, the block interleaves each phase of coefficients over a single FIR filter to share resources between phases. The single FIR filter has a serial architecture and uses the NumCycles value to share multipliers over time. A partly serial filter uses FilterLength/NumCycles multipliers. When NumCycles is greater than the filter length, the filter becomes fully serial and uses one multiplier. The diagram shows a filter with an interpolation factor of 4 and at least FilterLength/4 cycles between input samples.
Architectures 3 and 4 — Partly serial polyphase filter bank.
Each subfilter of the polyphase decomposition uses the NumCycles value to implement a serial filter. When NumCycles is FilterLength/InterpolationFactor, each phase uses a single multiplier, for a total of InterpolationFactor multipliers. The output is a vector if NumCycles < InterpolationFactor and a scalar if NumCycles ≥ InterpolationFactor.
The diagram shows a polyphase filter bank with scalar input and InterpolationFactor is set to 4. NumCycles is 2. Each subfilter is partly serial and has FilterLength/(4*2) multipliers, for a total of FilterLength/2 multipliers. The output is a vector because the interpolation factor is larger than the number of cycles between input samples.
Architectures 5 and 6 — Fully parallel polyphase filter bank.
The diagram shows the polyphase filter bank with scalar input and InterpolationFactor is set to 4. The NumCycles value is 1, so the output must be a vector and each subfilter contributes one sample to the output vector. Each subfilter is a fully parallel FIR filter, with L/4 multipliers, for a total of L multipliers.
When the input is a vector, each subfilter is a framebased filter that contains one parallel filter for each input sample. This diagram shows the polyphase filter bank for an input vector of two values and InterpolationFactor is set to 4. Each of the four subfilters generates two samples of the output vector and contains L/4*2 multipliers, for a total of L*2 multipliers.
Each subfilter is implemented with a Discrete FIR Filter block. For architecture details, see FIR Filter Architectures for FPGAs and ASICs.
Performance
This table shows the postsynthesis resource utilization for the HDL code generated for
the default FIR interpolation filter using scalar input, an interpolation factor of two,
16bit input, and 16bit coefficients. The synthesis targets a Xilinx ZC706 (XC7Z045ffg9002) FPGA. The Global HDL reset type
parameter is Synchronous
, and the Minimize clock
enables parameter is selected. The reset port is disabled,
so only the control path registers are connected to the generated global HDL reset.
Resource  Uses 

LUT  18 
FF  353 
BRAM  0 
Xilinx LogiCORE DSP48  72 
After place and route, the maximum clock frequency of the design is 455 MHz.
For the same filter configuration but with a fourelement input vector, the filter uses these resources.
Resource  Uses 

LUT  2080 
FF  6416 
BRAM  0 
Xilinx LogiCORE DSP48  288 
After place and route, the maximum clock frequency of the design is 385 MHz.
For a design with scalar input, an interpolation factor of four, and Minimum number of cycles between valid input samples set to four, the filter uses these resources. You can see the effect of sharing filter resources over the invalid cycles between input samples.
Resource  Uses 

LUT  1100 
FF  2258 
BRAM  0 
Xilinx LogiCORE DSP48  24 
After place and route, the maximum clock frequency of the design is 540 MHz.
Extended Capabilities
C/C++ Code Generation
Generate C and C++ code using Simulink® Coder™.
This block supports C/C++ code generation for Simulink accelerator and rapid accelerator modes and for DPI component generation.
HDL Code Generation
Generate VHDL, Verilog and SystemVerilog code for FPGA and ASIC designs using HDL Coder™.
HDL Coder™ provides additional configuration options that affect HDL implementation and synthesized logic.
ConstrainedOutputPipeline  Number of registers to place at
the outputs by moving existing delays within your design. Distributed
pipelining does not redistribute these registers. The default is

InputPipeline  Number of input pipeline stages
to insert in the generated code. Distributed pipelining and constrained
output pipelining can move these registers. The default is

OutputPipeline  Number of output pipeline stages
to insert in the generated code. Distributed pipelining and constrained
output pipelining can move these registers. The default is

Version History
Introduced in R2022aR2022b: Increased resource sharing for FIR Interpolator
Starting in R2022b, when Minimum number of cycles between valid input
samples is greater than the filter length, the block interleaves the
coefficients to share multipliers between the polyphase branches. To implement the filter
with the minimum number of multipliers, set Minimum number of cycles between valid
input samples to Inf
.
In R2022a, the minimum number of multipliers that a partly serial FIR interpolator could use was InterpolationFactor multipliers, which occurred when Minimum number of cycles between valid input samples was equal to the filter length. Increasing Minimum number of cycles between valid input samples above the filter length resulted in no additional resource sharing.
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