FIR Interpolator
Libraries:
DSP HDL Toolbox /
Filtering
Description
The FIR Interpolator block implements a single-rate polyphase FIR interpolation filter that is optimized for HDL code generation. The block provides a hardware-friendly interface with input and output control signals. To provide a cycle-accurate simulation of the generated HDL code, the block models architectural latency including pipeline registers and resource sharing.
The block accepts scalar or vector input and outputs a scalar or vector depending on the interpolation factor and the number of cycles between input samples. The block implements a polyphase decomposition with InterpolationFactor subfilters. The filter can implement a serial architecture if there is regular spacing between input samples.
The block provides two filter structures. The direct form systolic architecture provides an implementation that makes efficient use of Intel® and Xilinx® DSP blocks. This architecture can be fully-parallel or serial. To use a serial architecture, the input samples must be spaced out with a regular number of invalid cycles between the valid samples. The direct form transposed architecture is a fully parallel implementation that is suitable for FPGA and ASIC applications. For a filter implementation that matches multipliers, pipeline registers, and pre-adders to the DSP configuration of your FPGA vendor, specify your target device when you generate HDL code.
All filter structures optimize hardware resources by sharing multipliers for symmetric or antisymmetric filters and by removing the multipliers for zero-valued coefficients such as in half-band filters and Hilbert transforms.
Note
You can also generate HDL code for this hardware-optimized algorithm, without creating a Simulink® model, by using the DSP HDL IP Designer app. The app provides the same interface and configuration options as the Simulink block.
Examples
Implement Digital Upconverter for FPGA
Design a digital upconverter (DUC) for LTE on FPGAs.
Ports
Input
Output
Parameters
Algorithms
The block implements a polyphase filter bank where the filter coefficients are decomposed into InterpolationFactor subfilters. If the filter length is not divisible by the Interpolation factor parameter value, then the block zero-pads the coefficients. When your input is regularly spaced, with two or more cycles between valid samples, as indicated by the Minimum number of cycles between valid input samples parameter, the filter can share multiplier resources in time.
This flow chart shows which filter architectures result from your parameter settings. It also shows the number of multipliers used by the filter implementation. The filter architecture depends on the input frame size, V, the interpolation factor, R, the number of cycles between valid input samples, N, and the number of filter coefficients, L. The architectures are in order from lowest resource use on the left, to higher resources on the right. The higher resource architectures are trading off resource use for higher throughput. Each architecture is described below the flow chart.
If the filter is symmetric and you select
Optimize symmetric coefficients, the architecture shares multipliers
for matching coefficients, so effectively L =
L/2. (since R2024b)
The number of multipliers shown in the flow chart is for filters with real input and real coefficients. For complex input, the filter uses three times as many multipliers.
Architectures 1 and 2 — Serial polyphase interleaved filter bank.
When NumCycles is greater than FilterLength/InterpolationFactor, the block interleaves each phase of coefficients over a single FIR filter to share resources between phases. The single FIR filter has a serial architecture and uses the NumCycles value to share multipliers over time. A partly serial filter uses FilterLength/NumCycles multipliers. When NumCycles is greater than the filter length, the filter becomes fully serial and uses one multiplier. The diagram shows a filter with an interpolation factor of 4 and at least FilterLength/4 cycles between input samples.
Architectures 3 and 4 — Partly serial polyphase filter bank.
Each subfilter of the polyphase decomposition uses the NumCycles value to implement a serial filter. When NumCycles is FilterLength/InterpolationFactor, each phase uses a single multiplier, for a total of InterpolationFactor multipliers. The output is a vector if NumCycles < InterpolationFactor and a scalar if NumCycles ≥ InterpolationFactor.
The diagram shows a polyphase filter bank with scalar input and InterpolationFactor is set to 4. NumCycles is 2. Each subfilter is partly serial and has FilterLength/(4*2) multipliers, for a total of FilterLength/2 multipliers. The output is a vector because the interpolation factor is larger than the number of cycles between input samples.
Architectures 5 and 6 — Fully parallel polyphase filter bank.
The diagram shows the polyphase filter bank with scalar input and InterpolationFactor is set to 4. The NumCycles value is 1, so the output must be a vector and each subfilter contributes one sample to the output vector. Each subfilter is a fully parallel FIR filter, with L/4 multipliers, for a total of L multipliers.
When the input is a vector, each subfilter is a frame-based filter that contains one parallel filter for each input sample. This diagram shows the polyphase filter bank for an input vector of two values and InterpolationFactor is set to 4. Each of the four subfilters generates two samples of the output vector and contains L/4*2 multipliers, for a total of L*2 multipliers.
Each subfilter is implemented with a Discrete FIR Filter block. For architecture details, see FIR Filter Architectures for FPGAs and ASICs.
