Reuse of System-Level Circuit Models in Mixed-Signal Verification

This paper discusses some challenges faced in mixed-signal verification of power management ICs. The analog/mixed-signal (AMS) system models that were developed to prove the architecture were then used to generate SystemVerilog DPI-C models for both the analog and digital portions of designs. Use of these models in downstream RTL and AMS simulation environments has been shown to reduce overall debug and verification time. This paper describes the process used to generate the SystemVerilog DPI-C models and incorporate them into the verification framework. It also discusses the limitations encountered and offers suggestions for further improvements.

This paper was presented at DVCon US 2025.