Higher Productivity with Integrated MATLAB and Synopsys VCS Verification Workflows
Overview
Many integrated circuit (IC) design teams developing silicon devices for applications such as signal processing, wireless communications, image processing, and controls rely on Synopsys VCS in their verification environments. The signal processing and control algorithms implemented in these devices are typically developed using MATLAB and Simulink. Now, MathWorks and Synopsys have collaborated to develop integrated verification workflows that cater to the needs of algorithm developers, hardware designers, and design verification engineers. These workflows aim to shorten verification cycles and enable the reuse of MATLAB and Simulink models throughout the IC development process.
In this webinar, engineers from MathWorks and Synopsys will demonstrate the use of verification workflows introduced in the R2025a release.
Highlights
- Algorithm verification: Utilize MATLAB and Simulink models as testbenches with the Device Under Test (DUT) running in VCS.
- Behavioral modeling for RTL designs: use MATLAB to add behavioral models to HDL designs during RTL design phases.
- Verification component generation: Learn how to generate verification components from MATLAB and Simulink models for verification in VCS environments. Learn about the latest performance technologies in VCS and integration with the Synopsys Verdi debug platform.
- RTL verification workflows: Explore workflows for verifying Register-Transfer Level (RTL) designs using HDL generation from MATLAB and Simulink.
Join us to discover how these integrated workflows can streamline your verification process and improve the efficiency of your IC development projects.
Please allow approximately 45 minutes to attend the presentation and Q&A session. We will be recording this webinar, so if you can't make it for the live broadcast, register and we will send you a link to watch it on-demand.
Note: By providing your contact information, you are granting MathWorks your consent to share your contact information with Synopsys, Inc. for purposes of marketing, sales, and event management.
About the Presenter
Eric Cigan is a principal product marketing manager at MathWorks for ASIC and FPGA verification. Prior to joining MathWorks, he held technical marketing roles at Mentor Graphics, MathStar, and AccelChip. Eric has coauthored a series of papers for the Design and Verification Conference (DVCon) and presented to Synopsys SNUG conferences on verification of digital and mixed-signal ICs. Eric earned BS and MS degrees in mechanical engineering from the Massachusetts Institute of Technology.
Taruna Reddy is a principal product manager at Synopsys for functional simulation. Prior to joining Synopsys, she held field applications and verification engineering positions at Mentor Graphics, Verilab and Xtreme-EDA. Taruna holds a MSEE from Clemson University and Bachelor of Technology degree from India.
