From SerDes System-Level Model to RTL: Generating and Verifying HDL for a Decision Feedback Equalizer

Channel distortion in communications and high-speed data transmission can cause received signals to differ from the original signal, resulting in errors and data loss. Attenuation, noise, and interference can significantly degrade the quality of information being transmitted. Advanced techniques are employed to mitigate these effects, recovering the original signal and ensuring reliable communication. Decision feedback equalizer (DFE) adaptation engines implemented in FPGAs or ASICs are one such technique.

As data rates continue to scale, conventional single-summing-node DFEs can face timing constraints. One effective alternative is the dual-summing-node DFE, which partitions processing across two summing nodes to relax speed requirements at the cost of increased architectural complexity.

In this webinar, we walk through a comprehensive methodology for taking a floating-point, system-level SerDes receiver model with a dual-summing-node DFE and converting it into bit-accurate, synthesizable HDL for FPGA or ASIC implementation. Using the MathWorks SerDes Toolbox together with HDL Coder and HDL Verifier, we’ll cover:

• The architecture and motivation behind dual-summing-node DFE designs
• The structure of the reference receiver model (DFECDR) and the adaptation engine
• Step-by-step refinement of the adaptation engine to prepare for HDL code generation
• Automated HDL generation, including model setup
• Verification using HDL cosimulation of the generated Verilog against the bit-accurate Simulink model to confirm equivalence
• Best practices, tradeoffs, and considerations when bridging algorithmic models to hardware realizations

Attendees will gain insight into how to go from a clean system-level SerDes model to RTL-ready code, all while preserving functional integrity and preparing for IBIS-AMI compatibility. This is ideal for engineers working on high-speed I/O, equalization, and SerDes adaptation engines who want to streamline the path from modeling to hardware, and for teams implementing SerDes designs in hardware in general. 

Please allow approximately 45 minutes to attend the presentation and Q&A session. We will be recording this webinar, so if you can't make it for the live broadcast, register and we will send you a link to watch it on-demand.

About the Presenters

Andy Zambell is a Senior Product Marketing Engineer for SerDes and Signal Integrity applications at MathWorks. Prior to joining MathWorks, Andy was a Signal Integrity Engineer at FCI USA LLC and Amphenol for a decade where he specialized in new product development and customer support of high-speed backplane connectors. He also was involved in the development of industry standards such as SAS, IEEE 802.3 and OIF CEI. He received a B.S. in Physics from Lebanon Valley College and an M.E. in Electrical Engineering from Penn State University.

Eric Cigan is a Principal Product Manager at MathWorks, where he leads the strategy for HDL code generation and integrated circuit (IC) verification products. Prior to joining MathWorks, he held technical marketing roles at Mentor Graphics, MathStar, and AccelChip, a pioneer in high-level synthesis from MATLAB code. Since 2022, he coauthored a series of DVCon US papers on integrating MATLAB and Simulink into semiconductor verification workflows. Eric earned Bachelor of Science and a Master of Science degrees in Mechanical Engineering from the Massachusetts Institute of Technology. He earned his master’s degree as a Draper Fellow at Draper Laboratory in Cambridge, Massachusetts.