From MATLAB to Optimized RTL and PPA Exploration Using HDL Coder and Cadence Stratus
Overview
In this webinar, MathWorks® and Cadence® will introduce you to an advanced High-Level Synthesis (HLS) workflow that transforms MATLAB code into highly optimized synthesizable SystemC code for ASIC designs. We will demonstrate how HDL Coder is used to convert MATLAB code into synthesizable SystemC code, which then serves as a primary input for the Stratus HLS tool by Cadence. This powerful workflow provides ASIC design teams with early and precise insights into Power-Performance-Area (PPA) metrics, facilitating an automated journey from MATLAB to optimized RTL.
Highlights
Attendees will gain valuable insights into how this seamless integration significantly reduces design timelines while achieving designs with unparalleled PPA. The seminar will guide you through the process of starting with a MATLAB floating-point design and testbench, transitioning to fixed-point representation, and generating synthesizable SystemC code. Following this, we will illustrate how Cadence Stratus efficiently produces RTL code and how to leverage Cadence® Genus™ Synthesis and Joules™ RTL Power Analysis to achieve accurate PPA results.
Don't miss this opportunity to learn about cutting-edge techniques that streamline the design process and enhance the quality of ASIC implementations starting from MATLAB.
Please allow approximately 45 minutes to attend the presentation and Q&A session. We will be recording this webinar, so if you can't make it for the live broadcast, register and we will send you a link to watch it on-demand.
About the Presenters
Jeff Roane
Product Management, Cadence
Jeff Roane is a Group Director of Product Management within Cadence’s Digital & Signoff Group. He has extensive experience in both semiconductor design and EDA having served in engineering and product management roles at Electronics, Semiconductor, and EDA companies including Texas Instruments, Synopsys, and Dell Technologies. Jeff has a BSEE from the University of Akron and holds four patents for System and method for automated electronic device design.
Sarmad Dahir
Sr. Principal Application Engineer, Cadence
Sarmad Dahir graduated from the Royal Institute of Technology (KTH), Stockholm, Sweden, in 2007 with a M.Sc. EE specializing in IC microelectronics design.
Currently serving as a Sr. Principal Engineer at Cadence Design Systems, Sarmad is supporting hardware front-end design and implementation tools, particularly specializing in Stratus High-Level Synthesis technology. Sarmad’s career includes experience from working as an ASIC/FPGA designer and verification engineer for IC industry leading companies such as Ericsson and Samsung.
Satish Kurahatti
Product Management, MathWorks
Satish Kurahatti is a Principal Product Manager at MathWorks leading HDL, FPGA/SoC & ASIC solutions. He has been at MathWorks for more than 10 years in different roles and previously worked at Amazon Web Services within EC2 group leading EDA vertical and Arm-based Graviton processors. Satish has a master’s degree in electrical engineering from the State University of New York at Buffalo and an MBA from the Stephan M. Ross School of Business at the University of Michigan Ann Arbor.
