MATLAB and Simulink Seminars

System-on-Chip Workflow Essentials – From Architecture to Deployment

Bern, Switzerland

Venue Start Date End Date
Welle 7 10 Feb 2026, 12:00 CET 10 Feb 2026, 17:00 CET

Overview

This hands-on workshop explores advanced workflows for System-on-Chip (SoC) design using MathWorks tools. Participants will learn how to model architectures, generate HDL and C code, and deploy algorithms on heterogeneous SoC platforms. Through practical demonstrations with MATLAB, Simulink, System Composer, Embedded Coder and HDL Coder, attendees will gain hands-on experience in accelerating development cycles, improving design quality, and integrating hardware-in-the-loop testing for FPGA and embedded processors.

Highlights

By the end of this hands-on workshop, participants will be able to:

  1. Understand SoC design challenges and the role of Model-Based Design and Model-Based Systems Engineering.
  2. Manage SoC models and system architecture effectively.
  3. Generate and deploy HDL and C code for FPGA and ARM cores.
  4. Profile and optimize SoC implementations for performance.
  5. Apply best practices for version control and project management.

Who Should Attend

  • FPGA Engineers
  • Software Engineers
  • System Architects
  • Project leaders

About the Presenter

Stephan van Beek
Senior Principal Application Engineer SoC/FPGA/MBSE

Christoph Kammer
Senior Application Engineer Robotics/Autonomous Systems

Agenda

Time Session Presenter

12:00

Networking lunch

 

13:00

Introduction

  • Roundtable discussion on SoC design flow challenges
  • Role of Model-Based Systems Engineering in SoC workflows

All

13:30

Fundamentals to Managing SoC Architecture Models

  • Organize and modularize designs using projects
  • Version control and configuration management
  • Apply interface management across subsystems

Christoph Kammer

14:15

System-Level Architecture and Requirements Handling

  • Getting started with architecture modelling
  • Architecture modelling and requirement traceability
  • Implement unit testing frameworks for robust verification

Stephan van Beek

15:00

Coffee Break

 

15:15

Automated Code Generation and Deployment

  • Generating target-aware C code for ARM cores
  • Profiling and real-time execution on SoC boards
  • Develop IP cores for SoC and FPGA

Stephan van Beek

16:30

Next steps

Ragu Hegde

Morning Private Sessions –
Tailored SoC/FPGA Discussions (11:00-12:00)

Before the main workshop kicks off, we’re offering exclusive one-on-one sessions with our technical experts to dive into your specific SoC or FPGA projects. These private consultations are a great opportunity to discuss design challenges, explore advanced workflows, and identify how MathWorks tools can accelerate your development. To secure your slot, simply reach out to your account manager and sign up today!

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