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# Documentation

## Multi-Loop Compensator Design

### When to Use Multi-Loop Compensator Design

In many applications, a single-loop design is not feasible. If you have a design with inner loops, you can use the SISO Design Tool to design a compensator that meets your specifications.

### Workflow for Multi-Loop Compensator Design

A typical procedure is to design the innermost loop on its own. You can use the SISO Design Tool to isolate the design on individual loops. When used this way, the tool ignores outer loop dynamics. Once the inner loop is designed, you can move on to the design of the outer loop compensator to achieve the desired closed-loop behavior. Position Control of a DC Motor shows an example of this procedure.

### Position Control of a DC Motor

Instead of controlling the angular rate of a DC motor, this example develops a control law for controlling the position (angle) of the motor shaft. The block diagram of the DC motor, as shown in the following figure, has an integrator added as an outer loop.

Block Diagram of the Position-Controlled DC Motor

The design goal for this example is the minimize the closed-loop step response settling time while maintaining an inner loop phase margin of at least 65º with maximum bandwidth.

For details on how to derive state-space and transfer function representations of a DC motor, see SISO Example: The DC Motor.

Designing a multi-loop compensator for a DC motor involves the following steps:

#### Developing a Mathematical Model of the DC Motor

These are the relevant physical constants:

```R=2.0            % Ohms
L = 0.5          % Henrys
Km=0.1; Kb = 0.1 % Torque and back emf constants
Kf= 0.2;         % Nms
J = 0.02         % kg.m^2/s^2
```

First, construct a state-space model of the DC motor with one input, the applied voltage (Va). The output is the angular rate w.

```h1 = tf(Km,[L,R]); % Armature
h2 = tf(1,[J, Kf]) % Equation of motion
dcm = ss(h2) *h1; % w = h2 cascaded with h1
dcm = feedback(dcm, Kb, 1, 1);% Closes back emf loop
```

Adapting the Model to SISO Tool Architecture

One possible choice for your architecture is this multi-loop configuration.

Comparing this architecture to the original Block Diagram of the Position-Controlled DC Motor, it is evident that the two do not match. Using block diagram algebra, you can manipulate the original figure into one that fits this architecture.

Position-Controlled DC Motor Rearchitected

To create this representation, add an integrator to get Θ, the angular displacement, and a pure differentiator in the inner loop's return path. The channel from Va to w is dcm(1), making it the appropriate channel for adding the integrator.

```G = dcm*tf(1,[1,0]) % Motor with integrator; output is theta.
C2 = tf('s') % Differentiator
```

#### Selecting the Architecture and Importing the Model

Open the SISO Design Tool by typing

```sisotool
```

at the MATLAB® prompt. Once the Controls & Estimation Tools Manager opens, click Control Architecture on the Architecture page. Select the multi-loop configuration with two compensators, C1 in the forward path and C2 in the inner feedback loop — located in the lower-right corner.

Control Architecture Window

Next, import the model parameters by clicking System Data on the Architecture tab. This opens the System Data dialog box. Set G to G from the workspace. Assume a perfect sensor and set H to 1. C1 and C2 are the gains you will use to design a compensator. Set C1 to 1 and C2 to C2 from the workspace. Your System Data dialog box should look like this.

#### Selecting SISO Design Graphical Editor Views

Once you have selected the multi-loop architecture, click the Graphical Tuning tab. Set the plot types as follows:

1. Open-Loop 1 to "Root-Locus"

2. Open-Loop 2 to "Open-Loop Bode"

Your Graphical Tuning page should look like this.

Graphical Tuning Page Set for DC Motor Multi-Loop Design

Click Show Design Plot to see the SISO Design Graphical editor.

#### Designing the Inner Loop

You are now in a position to do the design. Start with the design of the inner loop. To do this, go to the Architecture page and remove the effects of the outer loop by following these steps:

1. Click Loop Configuration. This opens the Open-Loop Configuration dialog box.

2. From the pull-down menu, select Open-Loop Output of C2.

3. Click Highlight feedback loop. This opens a figure of the control architecture showing the loop configuration.

Notice how the C1 piece of the compensator and the outer loop are grayed out. This means that they will have no effect on the inner loop at this time.

Next, turn to the SISO Design Graphical editor. Use the Bode plot for open loop 2 (the inner loop) and increase the gain to maximize bandwidth subject to a 65º phase margin. This turns out to be a gain of about 16.1 for C2.

Setting the Inner Loop Gain

This finishes the design of the inner loop.

#### Tuning the Outer Loop

The goal in designing the outer loop is to minimize the settling time. Note that the outer loop can "see" the inner loop, so that the tuning affects the entire system. Follow these steps:

1. Go to the Analysis Plot tab in the Controls & Estimation Tools Manager. Select the Closed-Loop r to y check box.

2. Select Step from the Plot 1 pull-down menu. This opens the LTI Viewer for SISO Design.

3. Right-click in the step response plot and select Characteristics>Settling Time. Your LTI Viewer should look like this.

Initial Step Response with Settling Time

The settling time is about 79 s.

Return to the SISO Design Graphical editor and increase the gain of C1 in the root locus plot. At a gain of about 90.2, you will see the complex pair of poles move toward a slower time constant as the third pole moves toward a faster one. You can view the trade-off in the LTI Viewer for SISO Design. As the gain is changed, the closed-loop step response changes.

The 90.2 gain seems to yield a good compromise between rise and settling time.

Final Gain Choice for C1

#### Validating the Design with the LTI Viewer for SISO Design

Turning back to the LTI Viewer for SISO Design, it is evident that the settling time is now much lower than the original 78.9 s.

With a settling time of about 0.8 s, and a phase margin of 65º in the inner loop, the design is complete.